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| Hauptseite > Publikationsdatenbank > Complementary Strained Si GAA Nanowire TFET Inverter With Suppressed Ambipolarity > print |
| Hauptseite > Publikationsdatenbank > Complementary Strained Si GAA Nanowire TFET Inverter With Suppressed Ambipolarity > print |
| 001 | 821167 | ||
| 005 | 20210129224817.0 | ||
| 024 | 7 | _ | |a 10.1109/LED.2016.2582041 |2 doi |
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| 024 | 7 | _ | |a 1558-0563 |2 ISSN |
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| 037 | _ | _ | |a FZJ-2016-06405 |
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| 100 | 1 | _ | |a Luong, Gia Vinh |0 P:(DE-Juel1)156277 |b 0 |e Corresponding author |
| 245 | _ | _ | |a Complementary Strained Si GAA Nanowire TFET Inverter With Suppressed Ambipolarity |
| 260 | _ | _ | |a New York, NY |c 2016 |b IEEE |
| 336 | 7 | _ | |a article |2 DRIVER |
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| 520 | _ | _ | |a In this letter, we present complementary tunneling field-effect transistors (CTFETs) based on strained Si with gate all around nanowire structures on a single chip. The main focus is to suppress the ambipolar behavior of the TFETs with a gate-drain underlap. Detailed device characterization and demonstration of a CTFET inverter show that the ambipolar current is successfully eliminated for both pand n-devices. The CTFET inverter transfer characteristics indicate maximum separation of the high/low level with a sharp transition (high voltage gain) at a Vdd down to 0.4 V. In addition, high noise margin levels of 40% of the applied Vdd are obtained. |
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| 773 | _ | _ | |a 10.1109/LED.2016.2582041 |g Vol. 37, no. 8, p. 950 - 953 |0 PERI:(DE-600)2034325-5 |n 8 |p 950 - 953 |t IEEE electron device letters |v 37 |y 2016 |x 1558-0563 |
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