Home > Publications database > A 4-GHz LC-Based Voltage Controlled Oscillator & Frequency Divider for use in Neutrino Experiments > print

001     824570
005     20250129092443.0
037 _ _ |a FZJ-2016-07140
041 _ _ |a English
100 1 _ |a Parkalian, Nina
|0 P:(DE-Juel1)164418
|b 0
|e Corresponding author
|u fzj
111 2 _ |a Analog 2016
|c Bremen
|d 2016-09-12 - 2016-09-14
|w Germany
245 _ _ |a A 4-GHz LC-Based Voltage Controlled Oscillator & Frequency Divider for use in Neutrino Experiments
260 _ _ |c 2016
336 7 _ |a Conference Paper
|0 33
|2 EndNote
336 7 _ |a Other
|2 DataCite
336 7 _ |a INPROCEEDINGS
|2 BibTeX
336 7 _ |a conferenceObject
|2 DRIVER
336 7 _ |a LECTURE_SPEECH
|2 ORCID
336 7 _ |a Conference Presentation
|b conf
|m conf
|0 PUB:(DE-HGF)6
|s 1481826034_2008
|2 PUB:(DE-HGF)
|x After Call
502 _ _ |c University of Duisburg-Essen
520 _ _ |a A low power, low phase noise and wide tuning range 4GHz LC-based voltage controlled oscillator (VCO) to be used in a phase locked loop for neutrino experiments is presented. The design process should consider the limitations on the maximum tolerable jitter of the clock that is generated in the PLL. The presented structure consists of VCO block followed by two frequency dividers. To achieve a linear characteristic over a wide frequency range, the VCO uses NMOS varactors to control the frequency. The circuit is fabricated in a TSMC 65nm CMOS technology. The power consumption from 1.2V power supply excluding 50Ω buffer stage equals to 6.9mW. Measurement results provide -94dBc/Hz phase noise at 1MHz offset frequency from 1GHz carrier frequency. The circuit features a tuning range of 360MHz at the output of dividers for a control voltage range from 0 to 0.8V.
536 _ _ |a 899 - ohne Topic (POF3-899)
|0 G:(DE-HGF)POF3-899
|c POF3-899
|f POF III
|x 0
700 1 _ |a Robens, Markus
|0 P:(DE-Juel1)156319
|b 1
|u fzj
700 1 _ |a Grewing, Christian
|0 P:(DE-Juel1)159350
|b 2
|u fzj
700 1 _ |a van Waasen, Stefan
|0 P:(DE-Juel1)142562
|b 3
|u fzj
856 4 _ |u https://juser.fz-juelich.de/record/824570/files/07584289.pdf
|y Restricted
856 4 _ |u https://juser.fz-juelich.de/record/824570/files/07584289.gif?subformat=icon
|x icon
|y Restricted
856 4 _ |u https://juser.fz-juelich.de/record/824570/files/07584289.jpg?subformat=icon-1440
|x icon-1440
|y Restricted
856 4 _ |u https://juser.fz-juelich.de/record/824570/files/07584289.jpg?subformat=icon-180
|x icon-180
|y Restricted
856 4 _ |u https://juser.fz-juelich.de/record/824570/files/07584289.jpg?subformat=icon-640
|x icon-640
|y Restricted
856 4 _ |u https://juser.fz-juelich.de/record/824570/files/07584289.pdf?subformat=pdfa
|x pdfa
|y Restricted
909 C O |o oai:juser.fz-juelich.de:824570
|p VDB
910 1 _ |a Forschungszentrum Jülich
|0 I:(DE-588b)5008462-8
|k FZJ
|b 0
|6 P:(DE-Juel1)164418
910 1 _ |a Forschungszentrum Jülich
|0 I:(DE-588b)5008462-8
|k FZJ
|b 1
|6 P:(DE-Juel1)156319
910 1 _ |a Forschungszentrum Jülich
|0 I:(DE-588b)5008462-8
|k FZJ
|b 2
|6 P:(DE-Juel1)159350
910 1 _ |a Forschungszentrum Jülich
|0 I:(DE-588b)5008462-8
|k FZJ
|b 3
|6 P:(DE-Juel1)142562
913 1 _ |a DE-HGF
|b Programmungebundene Forschung
|l ohne Programm
|1 G:(DE-HGF)POF3-890
|0 G:(DE-HGF)POF3-899
|2 G:(DE-HGF)POF3-800
|v ohne Topic
|x 0
|4 G:(DE-HGF)POF
|3 G:(DE-HGF)POF3
914 1 _ |y 2016
920 1 _ |0 I:(DE-Juel1)ZEA-2-20090406
|k ZEA-2
|l Zentralinstitut für Elektronik
|x 0
980 _ _ |a conf
980 _ _ |a VDB
980 _ _ |a I:(DE-Juel1)ZEA-2-20090406
980 _ _ |a UNRESTRICTED
981 _ _ |a I:(DE-Juel1)PGI-4-20110106

LibraryCollectionCLSMajorCLSMinorLanguageAuthor
Marc 21