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@ARTICLE{SchulteBraucks:825768,
      author       = {Schulte-Braucks, C. and von den Driesch, N. and Glass, S.
                      and Tiedemann, Andreas and Breuer, Uwe and Besmehn, A. and
                      Hartmann, J.-M. and Ikonic, Z. and Zhao, Qing-Tai and Mantl,
                      S. and Buca, D.},
      title        = {{L}ow {T}emperature {D}eposition of {H}igh-k/{M}etal {G}ate
                      {S}tacks on {H}igh-{S}n {C}ontent ({S}i){G}e{S}n-{A}lloys},
      journal      = {ACS applied materials $\&$ interfaces},
      volume       = {8},
      number       = {20},
      issn         = {1944-8244},
      address      = {Washington, DC},
      publisher    = {Soc.},
      reportid     = {FZJ-2017-00073},
      pages        = {13133 - 13139},
      year         = {2016},
      abstract     = {(Si)GeSn is an emerging group IV alloy system offering new
                      exciting properties, with great potential for low power
                      electronics due to the fundamental direct band gap and
                      prospects as high mobility material. In this Article, we
                      present a systematic study of HfO2/TaN high-k/metal gate
                      stacks on (Si)GeSn ternary alloys and low temperature
                      processes for large scale integration of Sn based alloys.
                      Our investigations indicate that SiGeSn ternaries show
                      enhanced thermal stability compared to GeSn binaries,
                      allowing the use of the existing Si technology. Despite the
                      multielemental interface and large Sn content of up to 14
                      atom $\%,$ the HfO2/(Si)GeSn capacitors show small frequency
                      dispersion and stretch-out. The formed TaN/HfO2/(Si)GeSn
                      capacitors present a low leakage current of 2 × 10–8
                      A/cm2 at −1 V and a high breakdown field of ∼8 MV/cm.
                      For large Sn content SiGeSn/GeSn direct band gap
                      heterostructures, process temperatures below 350 °C are
                      required for integration. We developed an atomic vapor
                      deposition process for TaN metal gate on HfO2 high-k
                      dielectric and validated it by resistivity as well as
                      temperature and frequency dependent capacitance–voltage
                      measurements of capacitors on SiGeSn and GeSn. The densities
                      of interface traps are deduced to be in the low 1012 cm–2
                      eV–1 range and do not depend on the Sn-concentration. The
                      new processes developed here are compatible with (Si)GeSn
                      integration in large scale applications.},
      cin          = {PGI-9 / JARA-FIT / ZEA-3},
      ddc          = {540},
      cid          = {I:(DE-Juel1)PGI-9-20110106 / $I:(DE-82)080009_20140620$ /
                      I:(DE-Juel1)ZEA-3-20090406},
      pnm          = {521 - Controlling Electron Charge-Based Phenomena
                      (POF3-521) / E2SWITCH - Energy Efficient Tunnel FET Switches
                      and Circuits (619509)},
      pid          = {G:(DE-HGF)POF3-521 / G:(EU-Grant)619509},
      typ          = {PUB:(DE-HGF)16},
      UT           = {WOS:000376825800068},
      doi          = {10.1021/acsami.6b02425},
      url          = {https://juser.fz-juelich.de/record/825768},
}