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@ARTICLE{Madia:825769,
      author       = {Madia, O. and Afanas'ev, V. V. and Cott, D. and Arimura, H.
                      and Schulte-Braucks, C. and Lin, H. C. and Buca, D. and von
                      den Driesch, Nils and Nyns, L. and Ivanov, T. and Cuypers,
                      D. and Stesmans, A.},
      title        = {{S}aturation {P}hoto-{V}oltage {M}ethodology for
                      {S}emiconductor/{I}nsulator {I}nterface {T}rap
                      {S}pectroscopy},
      journal      = {ECS journal of solid state science and technology},
      volume       = {5},
      number       = {4},
      issn         = {2162-8777},
      address      = {Pennington, NJ},
      publisher    = {ECS},
      reportid     = {FZJ-2017-00074},
      pages        = {P3031 - P3036},
      year         = {2016},
      abstract     = {The presence of large densities of electrically active
                      defects is still an unsolved issue for future
                      high-mobility/high-k CMOS device technologies. This relates
                      to degraded device performance and reliability. Regrettably,
                      conventional admittance-based characterization techniques
                      often fail when applied to non-Si based devices. Among
                      others, enhanced generation of minority carriers and much
                      longer defect time constants make their results inaccurate.
                      Rather than of seeking to adapt commonly-used techniques, we
                      instead aim at direct measuring the semiconductor surface
                      potential by means of the Saturation surface PhotoVoltage
                      (SPV) technique. This approach allows for a DIT estimation
                      which is not limited by the trap response time or hindered
                      by minority carrier generation. Moreover, the DIT can be
                      estimated over the whole bandgap regardless of sample doping
                      type. We here report several case studies in support of the
                      proposed approach. We will also show that SPV can be applied
                      for the characterization of multi-layered Ge and III-V
                      devices incorporating high-k insulators.},
      cin          = {PGI-9},
      ddc          = {540},
      cid          = {I:(DE-Juel1)PGI-9-20110106},
      pnm          = {521 - Controlling Electron Charge-Based Phenomena
                      (POF3-521)},
      pid          = {G:(DE-HGF)POF3-521},
      typ          = {PUB:(DE-HGF)16},
      UT           = {WOS:000373212500007},
      doi          = {10.1149/2.0061604jss},
      url          = {https://juser.fz-juelich.de/record/825769},
}