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000826429 1001_ $$0P:(DE-HGF)0$$aLiu, Chang$$b0$$eCorresponding author
000826429 245__ $$aExperimental $I$ – $V(T)$ and $C$ – $V$ Analysis of Si Planar p-TFETs on Ultrathin Body
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000826429 520__ $$aWe present the experimental analysis of planar Si p-tunnel FETs (TFETs) fabricated on ultrathin body Silicon on Insulator (SOI) substrates by an optimized dopant implantation into silicide process. The average subthreshold swing of such planar TFETs reaches 75 mV/decade over four orders of magnitude of drain current. Emphasis is placed on the capacitance- voltage analysis of TFETs. In contrast to simulation predictions, we provide experimental evidence that the contribution of Cgs to the total gate capacitance increases at on-state, which in turn results in a decrease of the gate-to-drain capacitance Cgd. This beneficial effect could result in a reduction of the Miller capacitance effect in TFETs-based circuits.
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000826429 7001_ $$0P:(DE-Juel1)165600$$aHan, Qinghua$$b1$$ufzj
000826429 7001_ $$0P:(DE-Juel1)165997$$aGlass, Stefan$$b2$$ufzj
000826429 7001_ $$0P:(DE-Juel1)156277$$aLuong, Gia Vinh$$b3$$ufzj
000826429 7001_ $$0P:(DE-Juel1)164261$$aNarimani, Keyvan$$b4$$ufzj
000826429 7001_ $$0P:(DE-Juel1)128639$$aTiedemann, Andreas$$b5
000826429 7001_ $$0P:(DE-Juel1)125583$$aFox, Alfred$$b6$$ufzj
000826429 7001_ $$0P:(DE-HGF)0$$aYu, Wenjie$$b7
000826429 7001_ $$0P:(DE-HGF)0$$aWang, Xi$$b8
000826429 7001_ $$0P:(DE-Juel1)128609$$aMantl, Siegfried$$b9$$ufzj
000826429 7001_ $$0P:(DE-Juel1)128649$$aZhao, Qing-Tai$$b10$$eCorresponding author
000826429 773__ $$0PERI:(DE-600)2028088-9$$a10.1109/TED.2016.2619740$$gVol. 63, no. 12, p. 5036 - 5040$$n12$$p5036 - 5040$$tIEEE transactions on electron devices$$v63$$x1557-9646$$y2016
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