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@ARTICLE{Liu:826429,
author = {Liu, Chang and Han, Qinghua and Glass, Stefan and Luong,
Gia Vinh and Narimani, Keyvan and Tiedemann, Andreas and
Fox, Alfred and Yu, Wenjie and Wang, Xi and Mantl, Siegfried
and Zhao, Qing-Tai},
title = {{E}xperimental ${I}$ – ${V}({T})$ and ${C}$ – ${V}$
{A}nalysis of {S}i {P}lanar p-{TFET}s on {U}ltrathin {B}ody},
journal = {IEEE transactions on electron devices},
volume = {63},
number = {12},
issn = {1557-9646},
address = {New York, NY},
publisher = {IEEE},
reportid = {FZJ-2017-00654},
pages = {5036 - 5040},
year = {2016},
abstract = {We present the experimental analysis of planar Si p-tunnel
FETs (TFETs) fabricated on ultrathin body Silicon on
Insulator (SOI) substrates by an optimized dopant
implantation into silicide process. The average subthreshold
swing of such planar TFETs reaches 75 mV/decade over four
orders of magnitude of drain current. Emphasis is placed on
the capacitance- voltage analysis of TFETs. In contrast to
simulation predictions, we provide experimental evidence
that the contribution of Cgs to the total gate capacitance
increases at on-state, which in turn results in a decrease
of the gate-to-drain capacitance Cgd. This beneficial effect
could result in a reduction of the Miller capacitance effect
in TFETs-based circuits.},
cin = {PGI-9 / JARA-FIT},
ddc = {620},
cid = {I:(DE-Juel1)PGI-9-20110106 / $I:(DE-82)080009_20140620$},
pnm = {521 - Controlling Electron Charge-Based Phenomena
(POF3-521)},
pid = {G:(DE-HGF)POF3-521},
typ = {PUB:(DE-HGF)16},
UT = {WOS:000389342200064},
doi = {10.1109/TED.2016.2619740},
url = {https://juser.fz-juelich.de/record/826429},
}