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000836990 1001_ $$0P:(DE-Juel1)169769$$aMeka, Rathnakar$$b0$$eCorresponding author$$ufzj
000836990 245__ $$aImplementation of a JTAG Verification Environment for a Complex Highly Integrated Real SoC Solution for a Neutrino Detector$$f- 2017-06-22
000836990 260__ $$aJülich$$bForschungszentrum Jülich GmbH Zentralbibliothek, Verlag$$c2017
000836990 300__ $$aXI, 64 p.
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000836990 3367_ $$2BibTeX$$aMASTERSTHESIS
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000836990 3367_ $$0PUB:(DE-HGF)19$$2PUB:(DE-HGF)$$aMaster Thesis$$bmaster$$mmaster$$s1509972546_25967
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000836990 4900_ $$aBerichte des Forschungszentrums Jülich$$v4402
000836990 502__ $$aUniv. Duisburg, Masterarbeit, 2017$$bMA$$cUniv. Duisburg$$d2017
000836990 520__ $$aThis master thesis work deals with the configuration, enabling for the verification and interpretation of the data for the application specific designed read-out Vulcan chip by means of MATLAB tool for applications. Vulcan chip is an advanced system-on-chip (SoC) also called as an analog-to-digital unit(ADU) and it is developed by the Central Institute of Engineering, Electronics and Analytics- Electronic Systems (ZEA-2), Forschungszentrum Jülich GmbH. This chip will be used in the Jiangmen Underground Neutrino Observatory (JUNO) detector project to preprocess and digitize the analog data generated by the applied Photomultiplier Tubes (PMTs) reacting on neutrino events.  A configuration system is needed to enable the verification of the designed chip and the digitized data has to be interpreted and verified. A JTAG communication protocol is implemented to investigate the configuration of the chip. At first, the theoretical fundamentals of the designed chip will be explained to provide the basic understanding of the designed chip. This includes the characteristics of the chip by means of the functionality of individual blocks, configuration interface and different data modes in the chip. Furthermore, a configuration system is implemented which will be used to configure the chip and enables it for verification. Moreover, the configuration libraries are implemented in MATLAB. These libraries enable the chip for verification and test the write and read operations of all configuration registers in the chip. The implemented configuration system and libraries successfully configures the chip and the configuration libraries will be used in further verification tests. Secondly, the data extraction algorithms are implemented in MATLAB to analyze the data indifferent modes for the chip. The algorithms are tested for different data modes and the results are included in the report. Finally, the created data extraction algorithms will be used in the automatic data acquisition and analysis environment for easy analysis of the data from the chip.
000836990 536__ $$0G:(DE-HGF)POF3-612$$a612 - Cosmic Matter in the Laboratory (POF3-612)$$cPOF3-612$$fPOF III$$x0
000836990 8564_ $$uhttps://juser.fz-juelich.de/record/836990/files/J%C3%BCl_4402_Rathnakar.pdf$$yOpenAccess
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000836990 9141_ $$y2017
000836990 9131_ $$0G:(DE-HGF)POF3-612$$1G:(DE-HGF)POF3-610$$2G:(DE-HGF)POF3-600$$3G:(DE-HGF)POF3$$4G:(DE-HGF)POF$$aDE-HGF$$bForschungsbereich Materie$$lMaterie und Universum$$vCosmic Matter in the Laboratory$$x0
000836990 9201_ $$0I:(DE-Juel1)ZEA-2-20090406$$kZEA-2$$lZentralinstitut für Elektronik$$x0
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