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@PHDTHESIS{Luong:838669,
      author       = {Luong, Gia Vinh},
      title        = {{G}ate-{A}ll-{A}round {S}ilicon {N}anowire {T}unnel {FET}s
                      for {L}ow {P}ower {A}pplications},
      volume       = {154},
      school       = {RWTH Aachen},
      type         = {Dr.},
      address      = {Jülich},
      publisher    = {Forschungszentrum Jülich GmbH Zentralbibliothek, Verlag},
      reportid     = {FZJ-2017-07235},
      isbn         = {978-3-95806-259-7},
      series       = {Schriften des Forschungszentrums Jülich. Reihe
                      Schlüsseltechnologien / Key Technologies},
      pages        = {II, 136 S.},
      year         = {2017},
      note         = {RWTH Aachen, Diss., 2017},
      abstract     = {In the era of portable electronic devices energy efficient
                      integrated circuits (ICs) are highly demanded where the
                      power consumption needs to be minimized by the reduction of
                      the supply voltage V$_{dd}$. Digitl ciruits based on the
                      contemplementary metal-oxide-semiconductor field effect
                      transistors (MOSFETs), however, owns a physical limit of the
                      minimum inverse sub-threshold slope (SS) of 60 mV/dec at
                      room temperature. As consequence, the reduction of V$_{dd}$
                      either leads to low ON-current or inceases the OFF-current
                      exponentally which in turn results in high power device
                      concept with the potential to replace MOSFETs in low power
                      applications. In comparson, TFETs can offer steeper
                      transition between of OFF and the ON-state (SS<60mV/dec)
                      since the current transport mechamism relies on band-to-band
                      tunneling. Within the framework of this thesis strained Si
                      gate-all-around (GAA) nanowire TFETs are
                      ddddddddddfabricated in order to achieve high tunneling
                      currents and small SS. Very small namowires, down to 5 mm in
                      thickness and down to 15 nm in width, are surrounded by
                      HfO$_{2}$/TiN as high-$\textit{k}$ dielectric and metal gate
                      to obtain optimal gate electrostatics for the device. Tilted
                      ion i mplantation into the performed thin epitaxial
                      NiSi$_{2}$ has been performed to benefit from dopant
                      segregation that results in sharper doping profile for
                      source and drain. Strained Si GAA nanowire p- and n-TFETs
                      have been characterized indicating comparable current
                      performance with 5 $\mu$A/$\mu$m at V$_{dd}$=0.5 V. SS below
                      69 mV/dec has been measured for the n-TFET for I$_{d}$ <
                      10$^{-4} \mu$m at V$_{ds}$ = 0.1 V at room temperature.
                      However, most of the switching characteristics of the TFETs
                      yield SS larger than the thermal limit. Trap-assisted
                      tunneling is found to be the main root cause. [...]},
      cin          = {PGI-9},
      cid          = {I:(DE-Juel1)PGI-9-20110106},
      pnm          = {899 - ohne Topic (POF3-899)},
      pid          = {G:(DE-HGF)POF3-899},
      typ          = {PUB:(DE-HGF)3 / PUB:(DE-HGF)11},
      urn          = {urn:nbn:de:0001-2017121328},
      url          = {https://juser.fz-juelich.de/record/838669},
}