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| 001 | 838669 | ||
| 005 | 20220930130134.0 | ||
| 020 | _ | _ | |a 978-3-95806-259-7 |
| 024 | 7 | _ | |2 Handle |a 2128/16209 |
| 024 | 7 | _ | |2 URN |a urn:nbn:de:0001-2017121328 |
| 024 | 7 | _ | |2 ISSN |a 1866-1807 |
| 037 | _ | _ | |a FZJ-2017-07235 |
| 041 | _ | _ | |a English |
| 100 | 1 | _ | |0 P:(DE-Juel1)156277 |a Luong, Gia Vinh |b 0 |e Corresponding author |u fzj |
| 245 | _ | _ | |a Gate-All-Around Silicon Nanowire Tunnel FETs for Low Power Applications |f - 2017-12-13 |
| 260 | _ | _ | |a Jülich |b Forschungszentrum Jülich GmbH Zentralbibliothek, Verlag |c 2017 |
| 300 | _ | _ | |a II, 136 S. |
| 336 | 7 | _ | |2 DataCite |a Output Types/Dissertation |
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| 336 | 7 | _ | |2 ORCID |a DISSERTATION |
| 336 | 7 | _ | |2 BibTeX |a PHDTHESIS |
| 336 | 7 | _ | |0 2 |2 EndNote |a Thesis |
| 336 | 7 | _ | |0 PUB:(DE-HGF)11 |2 PUB:(DE-HGF) |a Dissertation / PhD Thesis |b phd |m phd |s 1513155618_1259 |
| 336 | 7 | _ | |2 DRIVER |a doctoralThesis |
| 490 | 0 | _ | |a Schriften des Forschungszentrums Jülich. Reihe Schlüsseltechnologien / Key Technologies |v 154 |
| 502 | _ | _ | |a RWTH Aachen, Diss., 2017 |b Dr. |c RWTH Aachen |d 2017 |
| 520 | _ | _ | |a In the era of portable electronic devices energy efficient integrated circuits (ICs) are highly demanded where the power consumption needs to be minimized by the reduction of the supply voltage V$_{dd}$. Digitl ciruits based on the contemplementary metal-oxide-semiconductor field effect transistors (MOSFETs), however, owns a physical limit of the minimum inverse sub-threshold slope (SS) of 60 mV/dec at room temperature. As consequence, the reduction of V$_{dd}$ either leads to low ON-current or inceases the OFF-current exponentally which in turn results in high power device concept with the potential to replace MOSFETs in low power applications. In comparson, TFETs can offer steeper transition between of OFF and the ON-state (SS<60mV/dec) since the current transport mechamism relies on band-to-band tunneling. Within the framework of this thesis strained Si gate-all-around (GAA) nanowire TFETs are ddddddddddfabricated in order to achieve high tunneling currents and small SS. Very small namowires, down to 5 mm in thickness and down to 15 nm in width, are surrounded by HfO$_{2}$/TiN as high-$\textit{k}$ dielectric and metal gate to obtain optimal gate electrostatics for the device. Tilted ion i mplantation into the performed thin epitaxial NiSi$_{2}$ has been performed to benefit from dopant segregation that results in sharper doping profile for source and drain. Strained Si GAA nanowire p- and n-TFETs have been characterized indicating comparable current performance with 5 $\mu$A/$\mu$m at V$_{dd}$=0.5 V. SS below 69 mV/dec has been measured for the n-TFET for I$_{d}$ < 10$^{-4} \mu$m at V$_{ds}$ = 0.1 V at room temperature. However, most of the switching characteristics of the TFETs yield SS larger than the thermal limit. Trap-assisted tunneling is found to be the main root cause. [...] |
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