001     838779
005     20230217105511.0
020 _ _ |a 978-3-95806-261-0
024 7 _ |2 Handle
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024 7 _ |2 ISSN
|a 1866-1777
037 _ _ |a FZJ-2017-07303
041 _ _ |a English
100 1 _ |0 P:(DE-Juel1)159348
|a Kim, Wonjoo
|b 0
|e Corresponding author
|u fzj
245 _ _ |a Investigation of switching mechanism in Ta$_{2}$O$_{5}$-based ReRAM devices
|f - 2017-12-06
260 _ _ |a Jülich
|b Forschungszentrum Jülich GmbH Zentralbibliothek, Verlag
|c 2017
300 _ _ |a II, III, II, 138 S.
336 7 _ |2 DataCite
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|a Thesis
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|s 1512546354_21213
336 7 _ |2 DRIVER
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490 0 _ |a Schriften des Forschungszentrums Jülich. Reihe Information / Information
|v 50
502 _ _ |a RWTH Aachen, Diss., 2017
|b Dissertation
|c RWTH Aachen
|d 2017
520 _ _ |a Redox-based Restive Random Access Memory (ReRAM) has recently receivedstrong attention due to its potential payout toward high density, low-cost,low-energy NVMs. Development and understanding of Ta$_{2}$O$_{5}$ based ReRAM devices in this research work have been made under following experiments, (i)Ta$_{2}$O$_{5}$ switching layer, (ii) ohmic electrode, (iii) Forming-free ReRAM devices, (iv)ReRAM and MOSFET integration, and (v) implementation of modular arithmetic function. In order to optimize the Ta$_{2}$O$_{5}$ switching layer, various approaches such as the effects of RF sputtering power in Ta$_{2}$O$_{5}$ deposition, the thickness effect of Ta$_{2}$O$_{5}$ switching layer, and the Bi-layer (Ta$_{2}$O$_{5}$ /TaO$_{x}$) structure have been made. The optimized 7 nm-thick Ta$_{2}$O$_{5}$ ReRAM device shows lower VFORM (1.8 V), reasonable V$_{S}$ET (0.8 V) with large memory window (R$_{OFF}$ /R$_{ON}$ >300 at V$_{RESET−STOP}$ =-2.0 V), stable endurance up to 106 cycles (@1.0 μs) and goodretention at 125 $^{\circ}$C for 10$^{4}$ seconds. Further, defect density in the switching oxide can also affect the switching properties of ReRAM devices and a modulation of defect density is possible by deposition rate variation. The layer deposition rate changes depending on RF sputtering power of Ta$_{2}$O$_{5}$ layer. The best RF power condition (236W) at given layer thickness (7 nm) was found in terms of memory window (R$_{OFF}$ /R$_{ON}$ > 800 at V$_{RESET−STOP}$ = -2.2 V) with high reliability (retention and endurance) performance. By introducing optimal Bi-layer (Ta$_{2}$O$_{5}$ /TaO$_{x}$) stack in Ta$_{2}$O$_{5}$ ReRAM device, the R$_{OFF}$ performance further improves with 7.0 nm-thick Ta$_{2}$O$_{5}$ / 20 nm-thick TaO$_{x}$ at low I$_{CC}$ level (50 μA) due to a better control of defects in the Ta$_{2}$O$_{5}$ switching layer. However, the V$_{FORM}$ of the Bi-layer increases from 1.8 V to 3.8 V in spite of highly conductive nature of TaO$_{x}$ layer. [...]
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