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001     840702
005     20230213130123.0
024 7 _ |a G:(EU-Grant)780215
|d 780215
|2 CORDIS
024 7 _ |a G:(EU-Call)H2020-ICT-2017-1
|d H2020-ICT-2017-1
|2 CORDIS
024 7 _ |a corda__h2020::780215
|2 originalID
035 _ _ |a G:(EU-Grant)780215
150 _ _ |a Computation-in-memory architecture based on resistive devices
|y 2018-01-01 - 2021-06-30
371 _ _ |a ARM LIMITED
|b ARM
|d United Kingdom
|v CORDIS
371 _ _ |a RWTH Aachen University
|b RWTH
|d Germany
|e http://www.rwth-aachen.de/cms/~a/root/lidx/1/
|v CORDIS
371 _ _ |a STICHTING IMEC NEDERLAND
|b IMEC-NL
|d Netherlands
|e http://www.holstcentre.com
|v CORDIS
371 _ _ |a Delft University of Technology
|b Delft University of Technology
|d Netherlands
|e http://www.tudelft.nl/en/
|v CORDIS
371 _ _ |a Swiss Federal Institute of Technology in Zurich
|b Swiss Federal Institute of Technology in Zurich
|d Switzerland
|e https://www.ethz.ch/en.html
|v CORDIS
371 _ _ |a IBM Research GmbH
|b IBM
|d Switzerland
|e http://www.zurich.ibm.com
|v CORDIS
371 _ _ |a INSTITUT NATIONAL DE RECHERCHE ENINFORMATIQUE ET AUTOMATIQUE
|b INRIA
|d France
|e http://www.inria.fr
|v CORDIS
371 _ _ |a INTELLIGENTSIA CONSULTANTS SARL
|b Intelligentsia Consultants
|d Luxembourg
|e http://www.intelligentsia-consultants.com
|v CORDIS
371 _ _ |a Eindhoven University of Technology
|b TU/e
|d Netherlands
|e http://www.tue.nl/
|v CORDIS
372 _ _ |a H2020-ICT-2017-1
|s 2018-01-01
|t 2021-06-30
450 _ _ |a MNEMOSENE
|w d
|y 2018-01-01 - 2021-06-30
510 1 _ |0 I:(DE-588b)5098525-5
|a European Union
|2 CORDIS
680 _ _ |a The MNEMOSENE project aims at demonstrating a new computation-in-memory (CIM) based on resistive devices together with its required programming flow and interface. To develop the new architecture, the following scientific and technical objectives will be targeted: • Objective 1: Develop new algorithmic solutions for targeted applications for CIM architecture. • Objective 2: Develop and design new mapping methods integrated in a framework for efficient compilation of the new algorithms into CIM macro-level operations; each of these is mapped to a group of CIM tiles. • Objective 3: Develop a macro-architecture based on the integration of group of CIM tiles, including the overall scheduling of the macro-level operation, data accesses, inter-tile communication, the partitioning of the crossbar, etc. • Objective 4: Develop and demonstrate the micro-architecture level of CIM tiles and their models, including primitive logic and arithmetic operators, the mapping of such operators on the crossbar, different circuit choices and the associated design trade-offs, etc. • Objective 5: Design a simulator (based on calibrated models of memristor devices & building blocks) and FPGA emulator for the new architecture (CIM device combined with conventional CPU) in order demonstrate its superiority. Demonstrate the concept of CIM by performing measurements on fabricated crossbar mounted on a PCB board. A demonstrator will be produced and tested to show that the storage and processing can be integrated in the same physical location to improve energy efficiency and also to show that the proposed accelerator is able to achieve the following measurable targets (as compared with a general purpose multi-core platform) for the considered applications: • Improve the energy-delay product by factor of 100X to 1000X • Improve the computational efficiency (#operations / total-energy) by factor of 10X to 100X • Improve the performance density (# operations per area) by factor of 10X to 100X
909 C O |o oai:juser.fz-juelich.de:840702
|p authority:GRANT
|p authority
970 _ _ |a oai:dnet:corda__h2020::53dd2a4babc9304020000c3367d95b4e
980 _ _ |a G
980 _ _ |a CORDIS
980 _ _ |a AUTHORITY

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