000843033 001__ 843033
000843033 005__ 20230210112514.0
000843033 0247_ $$2CORDIS$$aG:(EU-Grant)779877$$d779877
000843033 0247_ $$2CORDIS$$aG:(EU-Call)H2020-ICT-2017-1$$dH2020-ICT-2017-1
000843033 0247_ $$2originalID$$acorda__h2020::779877
000843033 035__ $$aG:(EU-Grant)779877
000843033 150__ $$aMont-Blanc 2020, European scalable, modular and power efficient HPC processor$$y2017-12-01 - 2021-03-31
000843033 371__ $$aBULL SAS$$bBULL$$dFrance$$ehttp://www.bull.com$$vCORDIS
000843033 371__ $$aKALRAY SA$$bKALRAY$$dFrance$$ehttp://www.kalray.eu$$vCORDIS
000843033 371__ $$aForschungszentrum Jülich$$bForschungszentrum Jülich$$dGermany$$ehttps://www.ptj.de/$$vCORDIS
000843033 371__ $$aARM LIMITED$$bARM$$dUnited Kingdom$$vCORDIS
000843033 371__ $$aAtomic Energy and Alternative Energies Commission$$bCEA$$dFrance$$ehttp://www.cea.fr/$$vCORDIS
000843033 371__ $$aSIPEARL$$dFrance$$ehttp://www.sipearl.com$$vCORDIS
000843033 371__ $$aSEMIDYNAMICS TECHNOLOGY SERVICES SL$$bSEMIDYNAMICS$$dSpain$$ehttp://www.semidynamics.com$$vCORDIS
000843033 371__ $$aBARCELONA SUPERCOMPUTING CENTER - CENTRO NACIONAL DE SUPERCOMPUTACION$$bBSC$$dSpain$$ehttp://www.bsc.es$$vCORDIS
000843033 372__ $$aH2020-ICT-2017-1$$s2017-12-01$$t2021-03-31
000843033 450__ $$aMont-Blanc 2020$$wd$$y2017-12-01 - 2021-03-31
000843033 5101_ $$0I:(DE-588b)5098525-5$$2CORDIS$$aEuropean Union
000843033 680__ $$aThe Mont-Blanc 2020 (MB2020) project ambitions to initiate the development of a future low-power European processor for Exascale. MB2020 lays the foundation for a European consortium aiming at delivering a processor with great energy efficiency for HPC and server workloads.  A first generation product is scheduled in the 2020 time frame.

Our target is to reach exascale-level power efficiency (50 Gflops/Watt at processor level) with a second generation planned for 2022. Therefore, we will, within MB2020: 
1. define a low-power System-on-Chip (SoC) implementation targeting Exascale, with built-in security and reliability features;
2. introduce strong innovations to improve efficiency with real-life applications and to outperform competition (vector instruction implementation, memory latency and bandwidth, power management, 2.5D integration);
3. develop key modules (IPs) needed for this implementation; 
4. provide a working prototype demonstrating MB2020 key components and system level simulations, with a co-design approach based on real-life applications;
5. explore the reuse of these building blocks to serve other markets than HPC. 

Our key choices are:
a) To use the ARM ISA (Instruction Set Architecture) because its has strong technological relevance and it offers a dynamic ecosystem, which is needed to deliver the system software and applications mandatory for successful market acceptance. 
b) To design, implement or leverage new technologies (Scalable Vector Extension, NoC, High Bandwidth Memory, Power Management, …) as well as innovative packaging technologies to improve the versatility, performance, power efficiency, reliability, and security of the processor.
c) To improve on the economic sustainability of processor development through a modular design that allows to retarget our SoC for different markets.
000843033 909CO $$ooai:juser.fz-juelich.de:843033$$pauthority$$pauthority:GRANT
000843033 970__ $$aoai:dnet:corda__h2020::9c5b95f91e1b0e49ce302ec1a1ec2400
000843033 980__ $$aG
000843033 980__ $$aCORDIS
000843033 980__ $$aAUTHORITY