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| 001 | 843033 | ||
| 005 | 20230210112514.0 | ||
| 024 | 7 | _ | |a G:(EU-Grant)779877 |d 779877 |2 CORDIS |
| 024 | 7 | _ | |a G:(EU-Call)H2020-ICT-2017-1 |d H2020-ICT-2017-1 |2 CORDIS |
| 024 | 7 | _ | |a corda__h2020::779877 |2 originalID |
| 035 | _ | _ | |a G:(EU-Grant)779877 |
| 150 | _ | _ | |a Mont-Blanc 2020, European scalable, modular and power efficient HPC processor |y 2017-12-01 - 2021-03-31 |
| 371 | _ | _ | |a BULL SAS |b BULL |d France |e http://www.bull.com |v CORDIS |
| 371 | _ | _ | |a KALRAY SA |b KALRAY |d France |e http://www.kalray.eu |v CORDIS |
| 371 | _ | _ | |a Forschungszentrum Jülich |b Forschungszentrum Jülich |d Germany |e https://www.ptj.de/ |v CORDIS |
| 371 | _ | _ | |a ARM LIMITED |b ARM |d United Kingdom |v CORDIS |
| 371 | _ | _ | |a Atomic Energy and Alternative Energies Commission |b CEA |d France |e http://www.cea.fr/ |v CORDIS |
| 371 | _ | _ | |a SIPEARL |d France |e http://www.sipearl.com |v CORDIS |
| 371 | _ | _ | |a SEMIDYNAMICS TECHNOLOGY SERVICES SL |b SEMIDYNAMICS |d Spain |e http://www.semidynamics.com |v CORDIS |
| 371 | _ | _ | |a BARCELONA SUPERCOMPUTING CENTER - CENTRO NACIONAL DE SUPERCOMPUTACION |b BSC |d Spain |e http://www.bsc.es |v CORDIS |
| 372 | _ | _ | |a H2020-ICT-2017-1 |s 2017-12-01 |t 2021-03-31 |
| 450 | _ | _ | |a Mont-Blanc 2020 |w d |y 2017-12-01 - 2021-03-31 |
| 510 | 1 | _ | |0 I:(DE-588b)5098525-5 |a European Union |2 CORDIS |
| 680 | _ | _ | |a The Mont-Blanc 2020 (MB2020) project ambitions to initiate the development of a future low-power European processor for Exascale. MB2020 lays the foundation for a European consortium aiming at delivering a processor with great energy efficiency for HPC and server workloads. A first generation product is scheduled in the 2020 time frame.
Our target is to reach exascale-level power efficiency (50 Gflops/Watt at processor level) with a second generation planned for 2022. Therefore, we will, within MB2020:
1. define a low-power System-on-Chip (SoC) implementation targeting Exascale, with built-in security and reliability features;
2. introduce strong innovations to improve efficiency with real-life applications and to outperform competition (vector instruction implementation, memory latency and bandwidth, power management, 2.5D integration);
3. develop key modules (IPs) needed for this implementation;
4. provide a working prototype demonstrating MB2020 key components and system level simulations, with a co-design approach based on real-life applications;
5. explore the reuse of these building blocks to serve other markets than HPC.
Our key choices are:
a) To use the ARM ISA (Instruction Set Architecture) because its has strong technological relevance and it offers a dynamic ecosystem, which is needed to deliver the system software and applications mandatory for successful market acceptance.
b) To design, implement or leverage new technologies (Scalable Vector Extension, NoC, High Bandwidth Memory, Power Management, …) as well as innovative packaging technologies to improve the versatility, performance, power efficiency, reliability, and security of the processor.
c) To improve on the economic sustainability of processor development through a modular design that allows to retarget our SoC for different markets. |
| 909 | C | O | |o oai:juser.fz-juelich.de:843033 |p authority:GRANT |p authority |
| 970 | _ | _ | |a oai:dnet:corda__h2020::9c5b95f91e1b0e49ce302ec1a1ec2400 |
| 980 | _ | _ | |a G |
| 980 | _ | _ | |a CORDIS |
| 980 | _ | _ | |a AUTHORITY |
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