%0 Conference Paper
%A Rigo, Alvise
%A Pinto, Christian
%A Pouget, Kevin
%A Raho, Daniel
%A Dutoit, Denis
%A Martinez, Pierre-Yves
%A Doran, Chris
%A Benini, Luca
%A Mavroidis, Iakovos
%A Marazakis, Manolis
%A Bartsch, Valeria
%A Lonsdale, Guy
%A Pop, Antoniu
%A Goodacre, John
%A Colliot, Annaik
%A Carpenter, Paul
%A Radojkovic, Petar
%A Pleiter, Dirk
%A Drouin, Dominique
%A Dinechin, Benoit Dupont de
%T Paving the Way Towards a Highly Energy-Efficient and Highly Integrated Compute Node for the Exascale Revolution: The ExaNoDe Approach
%I IEEE
%M FZJ-2018-01203
%P 486-493
%D 2017
%X Power consumption and high compute density are the key factors to be considered when building a compute node for the upcoming Exascale revolution. Current architectural design and manufacturing technologies are not able to provide the requested level of density and power efficiency to realise an operational Exascale machine. A disruptive change in the hardware design and integration process is needed in order to cope with the requirements of this forthcoming computing target. This paper presents the ExaNoDe H2020 research project aiming to design a highly energy efficient and highly integrated heterogeneous compute node targeting Exascale level computing, mixing low-power processors, heterogeneous co-processors and using advanced hardware integration technologies with the novel UNIMEM Global Address Space memory system.
%B 2017 Euromicro Conference on Digital System Design (DSD)
%C 30 Aug 2017 - 1 Sep 2017, Vienna (Austria)
Y2 30 Aug 2017 - 1 Sep 2017
M2 Vienna, Austria
%F PUB:(DE-HGF)8
%9 Contribution to a conference proceedings
%U <Go to ISI:>//WOS:000427097100070
%R 10.1109/DSD.2017.37
%U https://juser.fz-juelich.de/record/843621