% IMPORTANT: The following is UTF-8 encoded.  This means that in the presence
% of non-ASCII characters, it will not work with BibTeX 0.99 or older.
% Instead, you should use an up-to-date BibTeX implementation like “bibtex8” or
% “biber”.

@ARTICLE{Parkalian:843650,
      author       = {Parkalian, N. and Robens, M. and Grewing, C. and Christ, V.
                      and Kruth, A. and Liebau, D. and Muralidharan, P. and
                      Nielinger, D. and Roth, C. and Yegin, U. and Zambanini, A.
                      and van Waasen, S.},
      title        = {{A} 4 {GH}z phase locked loop design in 65 nm {CMOS} for
                      the {J}iangmen {U}nderground {N}eutrino {O}bservatory
                      detector},
      journal      = {Journal of Instrumentation},
      volume       = {13},
      number       = {02},
      issn         = {1748-0221},
      publisher    = {Journal of Instrumentation},
      reportid     = {FZJ-2018-01222},
      pages        = {P02010 - P02010},
      year         = {2018},
      abstract     = {This paper presents a 4 GHz phase locked loop (PLL), which
                      is implemented in a 65 nm standard CMOS process to provide
                      low noise and high frequency sampling clocks for readout
                      electronics to be used in the Jiangmen Underground Neutrino
                      Observatory (JUNO) experiment. Based on the application
                      requirements the target of the design is to find the best
                      compromise between power consumption, area and phase noise
                      for a highly reliable topology. The design implements a
                      novel method for the charge pump that suppresses current
                      mismatch when the PLL is locked. This reduces static phase
                      offset at the inputs of the phase-frequency detector (PFD)
                      that otherwise would introduce spurs at the PLL output. In
                      addition, a technique of amplitude regulation for the
                      voltage controlled oscillator (VCO) is presented to provide
                      low noise and reliable operation. The combination of thin
                      and thick oxide varactor transistors ensures optimum tuning
                      range and linearity over process as well as temperature
                      changes for the VCO without additional calibration steps.
                      The current mismatch at the output of the charge pump for
                      the control voltage at about half the 1 V supply voltage is
                      below $0.3\%$ and static phase offset down to $0.25\%$ is
                      reached. The total PLL consumes 18.5 mW power at 1.8 V
                      supply for the VCO and 1 V supply for the other parts.},
      cin          = {ZEA-2},
      ddc          = {610},
      cid          = {I:(DE-Juel1)ZEA-2-20090406},
      pnm          = {632 - Detector technology and systems (POF3-632) / 612 -
                      Cosmic Matter in the Laboratory (POF3-612) / FOR 2319 -
                      Bestimmung der Neutrino-Massenhierarchie mit dem
                      JUNO-Experiment (268668443)},
      pid          = {G:(DE-HGF)POF3-632 / G:(DE-HGF)POF3-612 /
                      G:(GEPRIS)268668443},
      typ          = {PUB:(DE-HGF)16},
      UT           = {WOS:000424627300002},
      doi          = {10.1088/1748-0221/13/02/P02010},
      url          = {https://juser.fz-juelich.de/record/843650},
}