%0 Journal Article
%A Luong, Gia Vinh
%A Strangio, S.
%A Tiedemann, Andreas
%A Bernardy, P.
%A Trellenkamp, Stefan
%A Palestri, P.
%A Mantl, S.
%A Zhao, Q. T.
%T Strained Silicon Complementary TFET SRAM: Experimental Demonstration and Simulations
%J IEEE journal of the Electron Devices Society
%V 6
%@ 2168-6734
%C [New York, NY]
%I IEEE
%M FZJ-2018-02292
%P 1033 - 1040
%D 2018
%X A half SRAM cell with strained Si nanowire complementary Tunnel-FETs (CTFET) was fabricated and characterized to explore the feasibility and functionality of 6T-SRAM based on TFETs. Outward-faced n-TFETs are used as access-transistors. Static measurements were performed to determine the SRAM butterfly curves, allowing the assessment of cell functionality and stability. The forward p-i-n leakage of the access-transistor at certain bias configurations leads to malfunctioning storage operation, even without the contribution of the ambipolar behavior. At large VDD, lowering of the bit-line bias is needed to mitigate such effect, demonstrating functional hold, read and write operations. Circuit simulations were carried out using a Verilog-A compact model calibrated on the experimental TFETs, providing a better understanding of the TFET SRAM operation at different supply voltages and for different cell sizing and giving an estimate of the dynamic performance of the cell.
%F PUB:(DE-HGF)16
%9 Journal Article
%U <Go to ISI:>//WOS:000443963500012
%R 10.1109/JEDS.2018.2825639
%U https://juser.fz-juelich.de/record/844953