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000844953 1001_ $$0P:(DE-HGF)0$$aLuong, Gia Vinh$$b0
000844953 245__ $$aStrained Silicon Complementary TFET SRAM: Experimental Demonstration and Simulations
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000844953 520__ $$aA half SRAM cell with strained Si nanowire complementary Tunnel-FETs (CTFET) was fabricated and characterized to explore the feasibility and functionality of 6T-SRAM based on TFETs. Outward-faced n-TFETs are used as access-transistors. Static measurements were performed to determine the SRAM butterfly curves, allowing the assessment of cell functionality and stability. The forward p-i-n leakage of the access-transistor at certain bias configurations leads to malfunctioning storage operation, even without the contribution of the ambipolar behavior. At large VDD, lowering of the bit-line bias is needed to mitigate such effect, demonstrating functional hold, read and write operations. Circuit simulations were carried out using a Verilog-A compact model calibrated on the experimental TFETs, providing a better understanding of the TFET SRAM operation at different supply voltages and for different cell sizing and giving an estimate of the dynamic performance of the cell.
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000844953 7001_ $$0P:(DE-HGF)0$$aStrangio, S.$$b1
000844953 7001_ $$0P:(DE-Juel1)128639$$aTiedemann, Andreas$$b2
000844953 7001_ $$0P:(DE-Juel1)138772$$aBernardy, P.$$b3
000844953 7001_ $$0P:(DE-Juel1)128856$$aTrellenkamp, Stefan$$b4
000844953 7001_ $$0P:(DE-HGF)0$$aPalestri, P.$$b5
000844953 7001_ $$0P:(DE-Juel1)128609$$aMantl, S.$$b6
000844953 7001_ $$0P:(DE-Juel1)128649$$aZhao, Q. T.$$b7$$eCorresponding author
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