TY  - JOUR
AU  - Luong, Gia Vinh
AU  - Strangio, S.
AU  - Tiedemann, Andreas
AU  - Bernardy, P.
AU  - Trellenkamp, Stefan
AU  - Palestri, P.
AU  - Mantl, S.
AU  - Zhao, Q. T.
TI  - Strained Silicon Complementary TFET SRAM: Experimental Demonstration and Simulations
JO  - IEEE journal of the Electron Devices Society
VL  - 6
SN  - 2168-6734
CY  - [New York, NY]
PB  - IEEE
M1  - FZJ-2018-02292
SP  - 1033 - 1040
PY  - 2018
AB  - A half SRAM cell with strained Si nanowire complementary Tunnel-FETs (CTFET) was fabricated and characterized to explore the feasibility and functionality of 6T-SRAM based on TFETs. Outward-faced n-TFETs are used as access-transistors. Static measurements were performed to determine the SRAM butterfly curves, allowing the assessment of cell functionality and stability. The forward p-i-n leakage of the access-transistor at certain bias configurations leads to malfunctioning storage operation, even without the contribution of the ambipolar behavior. At large VDD, lowering of the bit-line bias is needed to mitigate such effect, demonstrating functional hold, read and write operations. Circuit simulations were carried out using a Verilog-A compact model calibrated on the experimental TFETs, providing a better understanding of the TFET SRAM operation at different supply voltages and for different cell sizing and giving an estimate of the dynamic performance of the cell.
LB  - PUB:(DE-HGF)16
UR  - <Go to ISI:>//WOS:000443963500012
DO  - DOI:10.1109/JEDS.2018.2825639
UR  - https://juser.fz-juelich.de/record/844953
ER  -