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001     844953
005     20220930130145.0
024 7 _ |a 10.1109/JEDS.2018.2825639
|2 doi
024 7 _ |a 2128/19674
|2 Handle
024 7 _ |a WOS:000443963500012
|2 WOS
037 _ _ |a FZJ-2018-02292
082 _ _ |a 620
100 1 _ |a Luong, Gia Vinh
|0 P:(DE-HGF)0
|b 0
245 _ _ |a Strained Silicon Complementary TFET SRAM: Experimental Demonstration and Simulations
260 _ _ |a [New York, NY]
|c 2018
|b IEEE
336 7 _ |a article
|2 DRIVER
336 7 _ |a Output Types/Journal article
|2 DataCite
336 7 _ |a Journal Article
|b journal
|m journal
|0 PUB:(DE-HGF)16
|s 1536757822_4839
|2 PUB:(DE-HGF)
336 7 _ |a ARTICLE
|2 BibTeX
336 7 _ |a JOURNAL_ARTICLE
|2 ORCID
336 7 _ |a Journal Article
|0 0
|2 EndNote
520 _ _ |a A half SRAM cell with strained Si nanowire complementary Tunnel-FETs (CTFET) was fabricated and characterized to explore the feasibility and functionality of 6T-SRAM based on TFETs. Outward-faced n-TFETs are used as access-transistors. Static measurements were performed to determine the SRAM butterfly curves, allowing the assessment of cell functionality and stability. The forward p-i-n leakage of the access-transistor at certain bias configurations leads to malfunctioning storage operation, even without the contribution of the ambipolar behavior. At large VDD, lowering of the bit-line bias is needed to mitigate such effect, demonstrating functional hold, read and write operations. Circuit simulations were carried out using a Verilog-A compact model calibrated on the experimental TFETs, providing a better understanding of the TFET SRAM operation at different supply voltages and for different cell sizing and giving an estimate of the dynamic performance of the cell.
536 _ _ |a 141 - Controlling Electron Charge-Based Phenomena (POF3-141)
|0 G:(DE-HGF)POF3-141
|c POF3-141
|f POF III
|x 0
536 _ _ |a 521 - Controlling Electron Charge-Based Phenomena (POF3-521)
|0 G:(DE-HGF)POF3-521
|c POF3-521
|f POF III
|x 1
536 _ _ |a E2SWITCH - Energy Efficient Tunnel FET Switches and Circuits (619509)
|0 G:(EU-Grant)619509
|c 619509
|f FP7-ICT-2013-11
|x 2
588 _ _ |a Dataset connected to CrossRef
700 1 _ |a Strangio, S.
|0 P:(DE-HGF)0
|b 1
700 1 _ |a Tiedemann, Andreas
|0 P:(DE-Juel1)128639
|b 2
700 1 _ |a Bernardy, P.
|0 P:(DE-Juel1)138772
|b 3
700 1 _ |a Trellenkamp, Stefan
|0 P:(DE-Juel1)128856
|b 4
700 1 _ |a Palestri, P.
|0 P:(DE-HGF)0
|b 5
700 1 _ |a Mantl, S.
|0 P:(DE-Juel1)128609
|b 6
700 1 _ |a Zhao, Q. T.
|0 P:(DE-Juel1)128649
|b 7
|e Corresponding author
773 _ _ |a 10.1109/JEDS.2018.2825639
|g p. 1 - 1
|0 PERI:(DE-600)2696552-5
|p 1033 - 1040
|t IEEE journal of the Electron Devices Society
|v 6
|y 2018
|x 2168-6734
856 4 _ |u https://juser.fz-juelich.de/record/844953/files/2018-04-10-Reprints-1-11453265981-Zhao.pdf
856 4 _ |y OpenAccess
|u https://juser.fz-juelich.de/record/844953/files/08335289.pdf
856 4 _ |x icon
|u https://juser.fz-juelich.de/record/844953/files/2018-04-10-Reprints-1-11453265981-Zhao.gif?subformat=icon
856 4 _ |x icon-1440
|u https://juser.fz-juelich.de/record/844953/files/2018-04-10-Reprints-1-11453265981-Zhao.jpg?subformat=icon-1440
856 4 _ |x icon-180
|u https://juser.fz-juelich.de/record/844953/files/2018-04-10-Reprints-1-11453265981-Zhao.jpg?subformat=icon-180
856 4 _ |x icon-640
|u https://juser.fz-juelich.de/record/844953/files/2018-04-10-Reprints-1-11453265981-Zhao.jpg?subformat=icon-640
856 4 _ |x pdfa
|u https://juser.fz-juelich.de/record/844953/files/2018-04-10-Reprints-1-11453265981-Zhao.pdf?subformat=pdfa
856 4 _ |y OpenAccess
|x pdfa
|u https://juser.fz-juelich.de/record/844953/files/08335289.pdf?subformat=pdfa
909 C O |o oai:juser.fz-juelich.de:844953
|p openaire
|p open_access
|p OpenAPC
|p driver
|p VDB
|p ec_fundedresources
|p openCost
|p dnbdelivery
910 1 _ |a Forschungszentrum Jülich
|0 I:(DE-588b)5008462-8
|k FZJ
|b 0
|6 P:(DE-HGF)0
910 1 _ |a Forschungszentrum Jülich
|0 I:(DE-588b)5008462-8
|k FZJ
|b 2
|6 P:(DE-Juel1)128639
910 1 _ |a Forschungszentrum Jülich
|0 I:(DE-588b)5008462-8
|k FZJ
|b 3
|6 P:(DE-Juel1)138772
910 1 _ |a Forschungszentrum Jülich
|0 I:(DE-588b)5008462-8
|k FZJ
|b 4
|6 P:(DE-Juel1)128856
910 1 _ |a Forschungszentrum Jülich
|0 I:(DE-588b)5008462-8
|k FZJ
|b 6
|6 P:(DE-Juel1)128609
910 1 _ |a Forschungszentrum Jülich
|0 I:(DE-588b)5008462-8
|k FZJ
|b 7
|6 P:(DE-Juel1)128649
913 1 _ |a DE-HGF
|l Future Information Technology - Fundamentals, Novel Concepts and Energy Efficiency (FIT)
|1 G:(DE-HGF)POF3-140
|0 G:(DE-HGF)POF3-141
|2 G:(DE-HGF)POF3-100
|v Controlling Electron Charge-Based Phenomena
|x 0
|4 G:(DE-HGF)POF
|3 G:(DE-HGF)POF3
|b Energie
913 1 _ |a DE-HGF
|b Key Technologies
|l Future Information Technology - Fundamentals, Novel Concepts and Energy Efficiency (FIT)
|1 G:(DE-HGF)POF3-520
|0 G:(DE-HGF)POF3-521
|2 G:(DE-HGF)POF3-500
|v Controlling Electron Charge-Based Phenomena
|x 1
|4 G:(DE-HGF)POF
|3 G:(DE-HGF)POF3
914 1 _ |y 2018
915 _ _ |a DBCoverage
|0 StatID:(DE-HGF)0150
|2 StatID
|b Web of Science Core Collection
915 _ _ |a DBCoverage
|0 StatID:(DE-HGF)1160
|2 StatID
|b Current Contents - Engineering, Computing and Technology
915 _ _ |a DBCoverage
|0 StatID:(DE-HGF)0501
|2 StatID
|b DOAJ Seal
915 _ _ |a DBCoverage
|0 StatID:(DE-HGF)0200
|2 StatID
|b SCOPUS
915 _ _ |a WoS
|0 StatID:(DE-HGF)0111
|2 StatID
|b Science Citation Index Expanded
915 _ _ |a OpenAccess
|0 StatID:(DE-HGF)0510
|2 StatID
915 _ _ |a DBCoverage
|0 StatID:(DE-HGF)0500
|2 StatID
|b DOAJ
915 _ _ |a DBCoverage
|0 StatID:(DE-HGF)0199
|2 StatID
|b Thomson Reuters Master Journal List
920 _ _ |l yes
920 1 _ |0 I:(DE-Juel1)PGI-9-20110106
|k PGI-9
|l Halbleiter-Nanoelektronik
|x 0
920 1 _ |0 I:(DE-82)080009_20140620
|k JARA-FIT
|l JARA-FIT
|x 1
980 _ _ |a journal
980 _ _ |a VDB
980 _ _ |a UNRESTRICTED
980 _ _ |a I:(DE-Juel1)PGI-9-20110106
980 _ _ |a I:(DE-82)080009_20140620
980 _ _ |a APC
980 1 _ |a APC
980 1 _ |a FullTexts

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