MAESTRO
Middleware for memory and data-awareness in workflows
| Coordinator | Swiss Federal Institute of Technology in Zurich ; APPENTRA SOLUTIONS SL ; SEAGATE SYSTEMS UK LIMITED ; CRAY COMPUTER GMBH ; Forschungszentrum Jülich ; European Centre for Medium-Range Weather Forecasts ; Atomic Energy and Alternative Energies Commission |
| Grant period | 2018-09-01 - 2021-11-30 |
| Funding body | European Union |
| Call number | H2020-FETHPC-2017 |
| Grant number | 801101 |
| Identifier | G:(EU-Grant)801101 |
Note: Maestro will build a data-aware and memory-aware middleware framework that addresses ubiquitous problems of data movement in complex memory hierarchies and at many levels of the HPC software stack.
Though HPC and HPDA applications pose a broad variety of efficiency challenges, it would be fair to say that the performance of both has become dominated by data movement through the memory and storage systems, as opposed to floating point computational capability. Despite this shift, current software technologies remain severely limited in their ability to optimise data movement. The Maestro project addresses what it sees as the two major impediments of modern HPC software:
1. Moving data through memory was not always the bottleneck. The software stack that HPC relies upon was built through decades of a different situation – when the cost of performing floating point operations (FLOPS) was paramount. Several decades of technical evolution built a software stack and programming models highly fit for optimising floating point operations but lacking in basic data handling functionality. We characterise the set of technical issues at missing data-awareness.
2. Software rightfully insulates users from hardware details, especially as we move higher up the software stack. But HPC applications, programming environments and systems software cannot make key data movement decisions without some understanding of the hardware, especially the increasingly complex memory hierarchy. With the exception of runtimes, which treat memory in a domain-specific manner, software typically must make hardware-neutral decisions which can often leave performance on the table . We characterise this issue as missing memory-awareness.
Maestro proposes a middleware framework that enables memory- and data-awareness.
Recent Publications
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Conference Presentation (Plenary/Keynote)
Pleiter, D. (Corresponding author)FZJ*
Computer Architectures and Technologies towards Exascale
2019Indo-German Workshop on Computational Mathematics, BangaloreBangalore, India, 2 Dec 2019 - 4 Dec 20192019-12-022019-12-04
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Conference Presentation (Plenary/Keynote)
Pleiter, D. (Corresponding author)FZJ*
HPC Systems in the Next Decade - What to Expect, When, Where
201924th International Conference on Computing in High Energy and Nuclear Physics, CHEP 2019, AdelaideAdelaide, Australia, 4 Nov 2019 - 8 Nov 20192019-11-042019-11-08
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Conference Presentation (Invited)
Pleiter, D. (Corresponding author)FZJ*
Maestro Project Introduction
2019EuroHPC Summit Week 2019, PoznańPoznań, Poland, 13 May 2019 - 18 May 20192019-05-132019-05-18
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