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| Hauptseite > Publikationsdatenbank > A Novel Gate-Normal Tunneling Field-Effect Transistor With Dual-Metal Gate > print |
| Hauptseite > Publikationsdatenbank > A Novel Gate-Normal Tunneling Field-Effect Transistor With Dual-Metal Gate > print |
| 001 | 851015 | ||
| 005 | 20220930130155.0 | ||
| 024 | 7 | _ | |a 10.1109/JEDS.2018.2864581 |2 doi |
| 024 | 7 | _ | |a 2128/19706 |2 Handle |
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| 037 | _ | _ | |a FZJ-2018-04729 |
| 082 | _ | _ | |a 620 |
| 100 | 1 | _ | |a Glass, Stefan |0 P:(DE-Juel1)165997 |b 0 |
| 245 | _ | _ | |a A Novel Gate-Normal Tunneling Field-Effect Transistor With Dual-Metal Gate |
| 260 | _ | _ | |a [New York, NY] |c 2018 |b IEEE |
| 336 | 7 | _ | |a article |2 DRIVER |
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| 336 | 7 | _ | |a Journal Article |0 0 |2 EndNote |
| 520 | _ | _ | |a In this combined experiment and simulation study we investigate a SiGe/Si based gatenormal tunneling field-effect transistor (TFET) with a pillar shaped contact to the tunneling junction which brings forth two significant advantages. The first, is improved electrostatics at the boundary of the tunneling junction which helps to diminish the influence of adverse tunneling paths, and thus, substantially sharpens the device turn on. The second, is a simplified fabrication of a dual-metal gate using a selfaligned process. We demonstrate the feasibility of the process and show the positive effect of a dual-metal gate in experiment. Overall the paper provides general guidelines for the improvement of the subthreshold swing in gate-normal TFETs which are not restrained to the material system. |
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| 700 | 1 | _ | |a Kato, Kimihiko |0 P:(DE-HGF)0 |b 1 |
| 700 | 1 | _ | |a Kibkalo, Lidia |0 P:(DE-Juel1)169107 |b 2 |
| 700 | 1 | _ | |a Hartmann, Jean-Michel |0 P:(DE-HGF)0 |b 3 |
| 700 | 1 | _ | |a Takagi, Shinichi |0 P:(DE-HGF)0 |b 4 |
| 700 | 1 | _ | |a Buca, Dan Mihai |0 P:(DE-Juel1)125569 |b 5 |
| 700 | 1 | _ | |a Mantl, Siegfried |0 P:(DE-Juel1)128609 |b 6 |
| 700 | 1 | _ | |a Qing-Tai, Zhao |0 P:(DE-Juel1)128649 |b 7 |e Corresponding author |
| 773 | _ | _ | |a 10.1109/JEDS.2018.2864581 |g Vol. 6, p. 1070 - 1076 |0 PERI:(DE-600)2696552-5 |p 1070 - 1076 |t IEEE journal of the Electron Devices Society |v 6 |y 2018 |x 2168-6734 |
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