000859062 001__ 859062
000859062 005__ 20210130000150.0
000859062 010__ $$a
000859062 020__ $$a978-1-5386-4811-7
000859062 020__ $$a9781538648100
000859062 020__ $$a9781538648124 (print)
000859062 0247_ $$2doi$$a10.1109/ULIS.2018.8354771
000859062 037__ $$aFZJ-2019-00013
000859062 041__ $$aEnglish
000859062 1001_ $$0P:(DE-Juel1)173033$$aLiu, Mingshan$$b0$$eCorresponding author
000859062 1112_ $$a2018 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon (EUROSOI-ULIS)$$cGranada$$d2018-03-19 - 2018-03-21$$wSpain
000859062 245__ $$aRealization of vertical Ge nanowires for gate-all-around transistors
000859062 260__ $$aPiscataway, NJ$$bIEEE$$c2018
000859062 29510 $$a[Ebook] EUROSOI-ULIS 2018 : 2018 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon (EUROSOI-ULIS) : Granada, March 19-21, 2018 / Gámiz, Francisco , Piscataway, NJ : IEEE, 2018,
000859062 300__ $$a1-3
000859062 3367_ $$2ORCID$$aCONFERENCE_PAPER
000859062 3367_ $$033$$2EndNote$$aConference Paper
000859062 3367_ $$2BibTeX$$aINPROCEEDINGS
000859062 3367_ $$2DRIVER$$aconferenceObject
000859062 3367_ $$2DataCite$$aOutput Types/Conference Paper
000859062 3367_ $$0PUB:(DE-HGF)8$$2PUB:(DE-HGF)$$aContribution to a conference proceedings$$bcontrib$$mcontrib$$s1547477531_23129
000859062 3367_ $$0PUB:(DE-HGF)7$$2PUB:(DE-HGF)$$aContribution to a book$$mcontb
000859062 520__ $$aTowards gate-all-around (GAA) FETs, we present the top-down realization of vertical Ge nanowires (NWs) with defect-free sidewall and perfect anisotropy. The NW patterns are transferred by a novel inductively coupled plasma reactive ion etching (ICP-RIE) technique. With optimized etching conditions, sub-60 nm diameter Ge nanowires are guaranteed while mitigating micro-trenching and under-cutting effects. To further shrink the NW diameter, digital etching is followed including multiple cycles of self-limited O2 plasma oxidation and diluted HF rinsing. O2 plasma is also utilized for surface passivation in Ge MOScaps to improve the high-k/Ge interface. These NWs form the base of vertical transistors which are simulated by TCAD tools here. The processing techniques proposed in this work provide a viable option for low power vertical Ge and GeSn NW transistors.
000859062 536__ $$0G:(DE-HGF)POF3-521$$a521 - Controlling Electron Charge-Based Phenomena (POF3-521)$$cPOF3-521$$fPOF III$$x0
000859062 588__ $$aDataset connected to CrossRef Conference
000859062 7001_ $$0P:(DE-Juel1)171699$$aMertens, K.$$b1$$ufzj
000859062 7001_ $$0P:(DE-HGF)0$$aGlass, S.$$b2
000859062 7001_ $$0P:(DE-Juel1)128609$$aMantl, S.$$b3$$ufzj
000859062 7001_ $$0P:(DE-Juel1)125569$$aBuca, D.$$b4$$ufzj
000859062 7001_ $$0P:(DE-Juel1)128649$$aZhao, Q. T.$$b5$$ufzj
000859062 7001_ $$0P:(DE-Juel1)128856$$aTrellenkamp, S.$$b6$$ufzj
000859062 773__ $$a10.1109/ULIS.2018.8354771
000859062 8564_ $$uhttps://juser.fz-juelich.de/record/859062/files/08354771.pdf$$yRestricted
000859062 8564_ $$uhttps://juser.fz-juelich.de/record/859062/files/08354771.pdf?subformat=pdfa$$xpdfa$$yRestricted
000859062 909CO $$ooai:juser.fz-juelich.de:859062$$pVDB
000859062 9101_ $$0I:(DE-588b)5008462-8$$6P:(DE-Juel1)173033$$aForschungszentrum Jülich$$b0$$kFZJ
000859062 9101_ $$0I:(DE-588b)5008462-8$$6P:(DE-Juel1)171699$$aForschungszentrum Jülich$$b1$$kFZJ
000859062 9101_ $$0I:(DE-588b)5008462-8$$6P:(DE-HGF)0$$aForschungszentrum Jülich$$b2$$kFZJ
000859062 9101_ $$0I:(DE-588b)5008462-8$$6P:(DE-Juel1)128609$$aForschungszentrum Jülich$$b3$$kFZJ
000859062 9101_ $$0I:(DE-588b)5008462-8$$6P:(DE-Juel1)125569$$aForschungszentrum Jülich$$b4$$kFZJ
000859062 9101_ $$0I:(DE-588b)5008462-8$$6P:(DE-Juel1)128649$$aForschungszentrum Jülich$$b5$$kFZJ
000859062 9101_ $$0I:(DE-588b)5008462-8$$6P:(DE-Juel1)128856$$aForschungszentrum Jülich$$b6$$kFZJ
000859062 9131_ $$0G:(DE-HGF)POF3-521$$1G:(DE-HGF)POF3-520$$2G:(DE-HGF)POF3-500$$3G:(DE-HGF)POF3$$4G:(DE-HGF)POF$$aDE-HGF$$bKey Technologies$$lFuture Information Technology - Fundamentals, Novel Concepts and Energy Efficiency (FIT)$$vControlling Electron Charge-Based Phenomena$$x0
000859062 9141_ $$y2018
000859062 9201_ $$0I:(DE-Juel1)PGI-9-20110106$$kPGI-9$$lHalbleiter-Nanoelektronik$$x0
000859062 980__ $$acontrib
000859062 980__ $$aVDB
000859062 980__ $$acontb
000859062 980__ $$aI:(DE-Juel1)PGI-9-20110106
000859062 980__ $$aUNRESTRICTED