TY  - CONF
AU  - Liu, Mingshan
AU  - Mertens, K.
AU  - Glass, S.
AU  - Mantl, S.
AU  - Buca, D.
AU  - Zhao, Q. T.
AU  - Trellenkamp, S.
TI  - Realization of vertical Ge nanowires for gate-all-around transistors
CY  - Piscataway, NJ
PB  - IEEE
M1  - FZJ-2019-00013
SN  - 978-1-5386-4811-7
SP  - 1-3
PY  - 2018
AB  - Towards gate-all-around (GAA) FETs, we present the top-down realization of vertical Ge nanowires (NWs) with defect-free sidewall and perfect anisotropy. The NW patterns are transferred by a novel inductively coupled plasma reactive ion etching (ICP-RIE) technique. With optimized etching conditions, sub-60 nm diameter Ge nanowires are guaranteed while mitigating micro-trenching and under-cutting effects. To further shrink the NW diameter, digital etching is followed including multiple cycles of self-limited O2 plasma oxidation and diluted HF rinsing. O2 plasma is also utilized for surface passivation in Ge MOScaps to improve the high-k/Ge interface. These NWs form the base of vertical transistors which are simulated by TCAD tools here. The processing techniques proposed in this work provide a viable option for low power vertical Ge and GeSn NW transistors.
T2  - 2018 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon (EUROSOI-ULIS)
CY  - 19 Mar 2018 - 21 Mar 2018, Granada (Spain)
Y2  - 19 Mar 2018 - 21 Mar 2018
M2  - Granada, Spain
LB  - PUB:(DE-HGF)8 ; PUB:(DE-HGF)7
DO  - DOI:10.1109/ULIS.2018.8354771
UR  - https://juser.fz-juelich.de/record/859062
ER  -