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@INPROCEEDINGS{Liu:859062,
      author       = {Liu, Mingshan and Mertens, K. and Glass, S. and Mantl, S.
                      and Buca, D. and Zhao, Q. T. and Trellenkamp, S.},
      title        = {{R}ealization of vertical {G}e nanowires for
                      gate-all-around transistors},
      address      = {Piscataway, NJ},
      publisher    = {IEEE},
      reportid     = {FZJ-2019-00013},
      isbn         = {978-1-5386-4811-7},
      pages        = {1-3},
      year         = {2018},
      comment      = {[Ebook] EUROSOI-ULIS 2018 : 2018 Joint International
                      EUROSOI Workshop and International Conference on Ultimate
                      Integration on Silicon (EUROSOI-ULIS) : Granada, March
                      19-21, 2018 / Gámiz, Francisco , Piscataway, NJ : IEEE,
                      2018,},
      booktitle     = {[Ebook] EUROSOI-ULIS 2018 : 2018 Joint
                       International EUROSOI Workshop and
                       International Conference on Ultimate
                       Integration on Silicon (EUROSOI-ULIS) :
                       Granada, March 19-21, 2018 / Gámiz,
                       Francisco , Piscataway, NJ : IEEE,
                       2018,},
      abstract     = {Towards gate-all-around (GAA) FETs, we present the top-down
                      realization of vertical Ge nanowires (NWs) with defect-free
                      sidewall and perfect anisotropy. The NW patterns are
                      transferred by a novel inductively coupled plasma reactive
                      ion etching (ICP-RIE) technique. With optimized etching
                      conditions, sub-60 nm diameter Ge nanowires are guaranteed
                      while mitigating micro-trenching and under-cutting effects.
                      To further shrink the NW diameter, digital etching is
                      followed including multiple cycles of self-limited O2 plasma
                      oxidation and diluted HF rinsing. O2 plasma is also utilized
                      for surface passivation in Ge MOScaps to improve the
                      high-k/Ge interface. These NWs form the base of vertical
                      transistors which are simulated by TCAD tools here. The
                      processing techniques proposed in this work provide a viable
                      option for low power vertical Ge and GeSn NW transistors.},
      month         = {Mar},
      date          = {2018-03-19},
      organization  = {2018 Joint International EUROSOI
                       Workshop and International Conference
                       on Ultimate Integration on Silicon
                       (EUROSOI-ULIS), Granada (Spain), 19 Mar
                       2018 - 21 Mar 2018},
      cin          = {PGI-9},
      cid          = {I:(DE-Juel1)PGI-9-20110106},
      pnm          = {521 - Controlling Electron Charge-Based Phenomena
                      (POF3-521)},
      pid          = {G:(DE-HGF)POF3-521},
      typ          = {PUB:(DE-HGF)8 / PUB:(DE-HGF)7},
      doi          = {10.1109/ULIS.2018.8354771},
      url          = {https://juser.fz-juelich.de/record/859062},
}