Home > Publications database > Realization of vertical Ge nanowires for gate-all-around transistors > print |
001 | 859062 | ||
005 | 20210130000150.0 | ||
010 | _ | _ | |a |
020 | _ | _ | |a 978-1-5386-4811-7 |
020 | _ | _ | |a 9781538648100 |
020 | _ | _ | |a 9781538648124 (print) |
024 | 7 | _ | |a 10.1109/ULIS.2018.8354771 |2 doi |
037 | _ | _ | |a FZJ-2019-00013 |
041 | _ | _ | |a English |
100 | 1 | _ | |a Liu, Mingshan |0 P:(DE-Juel1)173033 |b 0 |e Corresponding author |
111 | 2 | _ | |a 2018 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon (EUROSOI-ULIS) |c Granada |d 2018-03-19 - 2018-03-21 |w Spain |
245 | _ | _ | |a Realization of vertical Ge nanowires for gate-all-around transistors |
260 | _ | _ | |a Piscataway, NJ |c 2018 |b IEEE |
295 | 1 | 0 | |a [Ebook] EUROSOI-ULIS 2018 : 2018 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon (EUROSOI-ULIS) : Granada, March 19-21, 2018 / Gámiz, Francisco , Piscataway, NJ : IEEE, 2018, |
300 | _ | _ | |a 1-3 |
336 | 7 | _ | |a CONFERENCE_PAPER |2 ORCID |
336 | 7 | _ | |a Conference Paper |0 33 |2 EndNote |
336 | 7 | _ | |a INPROCEEDINGS |2 BibTeX |
336 | 7 | _ | |a conferenceObject |2 DRIVER |
336 | 7 | _ | |a Output Types/Conference Paper |2 DataCite |
336 | 7 | _ | |a Contribution to a conference proceedings |b contrib |m contrib |0 PUB:(DE-HGF)8 |s 1547477531_23129 |2 PUB:(DE-HGF) |
336 | 7 | _ | |a Contribution to a book |0 PUB:(DE-HGF)7 |2 PUB:(DE-HGF) |m contb |
520 | _ | _ | |a Towards gate-all-around (GAA) FETs, we present the top-down realization of vertical Ge nanowires (NWs) with defect-free sidewall and perfect anisotropy. The NW patterns are transferred by a novel inductively coupled plasma reactive ion etching (ICP-RIE) technique. With optimized etching conditions, sub-60 nm diameter Ge nanowires are guaranteed while mitigating micro-trenching and under-cutting effects. To further shrink the NW diameter, digital etching is followed including multiple cycles of self-limited O2 plasma oxidation and diluted HF rinsing. O2 plasma is also utilized for surface passivation in Ge MOScaps to improve the high-k/Ge interface. These NWs form the base of vertical transistors which are simulated by TCAD tools here. The processing techniques proposed in this work provide a viable option for low power vertical Ge and GeSn NW transistors. |
536 | _ | _ | |a 521 - Controlling Electron Charge-Based Phenomena (POF3-521) |0 G:(DE-HGF)POF3-521 |c POF3-521 |f POF III |x 0 |
588 | _ | _ | |a Dataset connected to CrossRef Conference |
700 | 1 | _ | |a Mertens, K. |0 P:(DE-Juel1)171699 |b 1 |u fzj |
700 | 1 | _ | |a Glass, S. |0 P:(DE-HGF)0 |b 2 |
700 | 1 | _ | |a Mantl, S. |0 P:(DE-Juel1)128609 |b 3 |u fzj |
700 | 1 | _ | |a Buca, D. |0 P:(DE-Juel1)125569 |b 4 |u fzj |
700 | 1 | _ | |a Zhao, Q. T. |0 P:(DE-Juel1)128649 |b 5 |u fzj |
700 | 1 | _ | |a Trellenkamp, S. |0 P:(DE-Juel1)128856 |b 6 |u fzj |
773 | _ | _ | |a 10.1109/ULIS.2018.8354771 |
856 | 4 | _ | |u https://juser.fz-juelich.de/record/859062/files/08354771.pdf |y Restricted |
856 | 4 | _ | |u https://juser.fz-juelich.de/record/859062/files/08354771.pdf?subformat=pdfa |x pdfa |y Restricted |
909 | C | O | |o oai:juser.fz-juelich.de:859062 |p VDB |
910 | 1 | _ | |a Forschungszentrum Jülich |0 I:(DE-588b)5008462-8 |k FZJ |b 0 |6 P:(DE-Juel1)173033 |
910 | 1 | _ | |a Forschungszentrum Jülich |0 I:(DE-588b)5008462-8 |k FZJ |b 1 |6 P:(DE-Juel1)171699 |
910 | 1 | _ | |a Forschungszentrum Jülich |0 I:(DE-588b)5008462-8 |k FZJ |b 2 |6 P:(DE-HGF)0 |
910 | 1 | _ | |a Forschungszentrum Jülich |0 I:(DE-588b)5008462-8 |k FZJ |b 3 |6 P:(DE-Juel1)128609 |
910 | 1 | _ | |a Forschungszentrum Jülich |0 I:(DE-588b)5008462-8 |k FZJ |b 4 |6 P:(DE-Juel1)125569 |
910 | 1 | _ | |a Forschungszentrum Jülich |0 I:(DE-588b)5008462-8 |k FZJ |b 5 |6 P:(DE-Juel1)128649 |
910 | 1 | _ | |a Forschungszentrum Jülich |0 I:(DE-588b)5008462-8 |k FZJ |b 6 |6 P:(DE-Juel1)128856 |
913 | 1 | _ | |a DE-HGF |b Key Technologies |l Future Information Technology - Fundamentals, Novel Concepts and Energy Efficiency (FIT) |1 G:(DE-HGF)POF3-520 |0 G:(DE-HGF)POF3-521 |2 G:(DE-HGF)POF3-500 |v Controlling Electron Charge-Based Phenomena |x 0 |4 G:(DE-HGF)POF |3 G:(DE-HGF)POF3 |
914 | 1 | _ | |y 2018 |
920 | 1 | _ | |0 I:(DE-Juel1)PGI-9-20110106 |k PGI-9 |l Halbleiter-Nanoelektronik |x 0 |
980 | _ | _ | |a contrib |
980 | _ | _ | |a VDB |
980 | _ | _ | |a contb |
980 | _ | _ | |a I:(DE-Juel1)PGI-9-20110106 |
980 | _ | _ | |a UNRESTRICTED |
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