%0 Journal Article
%A Narimani, K.
%A Glass, S.
%A Bernardy, P.
%A von den Driesch, N.
%A Zhao, Q. T.
%A Mantl, S.
%T Silicon tunnel FET with average subthreshold slope of 55 mV/dec at low drain currents
%J Solid state electronics
%V 143
%@ 0038-1101
%C Oxford [u.a.]
%I Pergamon, Elsevier Science
%M FZJ-2019-00015
%P 62 - 68
%D 2018
%X In this paper we present a silicon tunnel FET based on line-tunneling to achieve better subthreshold performance. The fabricated device shows an on-current of Ion = 2.55 × 10−7 A/µm at Vds = Von = Vgs − Voff = −0.5 V for an Ioff = 1 nA/µm and an average SS of 55 mV/dec over two orders of magnitude of Id. Furthermore, the analog figures of merit have been calculated and show that the transconductance efficiency gm/Id beats the MOSFET performance at low currents.
%F PUB:(DE-HGF)16
%9 Journal Article
%U <Go to ISI:>//WOS:000430550600010
%R 10.1016/j.sse.2018.01.007
%U https://juser.fz-juelich.de/record/859064