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| 001 | 859064 | ||
| 005 | 20210130000151.0 | ||
| 024 | 7 | _ | |a 10.1016/j.sse.2018.01.007 |2 doi |
| 024 | 7 | _ | |a 0038-1101 |2 ISSN |
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| 100 | 1 | _ | |a Narimani, K. |0 P:(DE-Juel1)164261 |b 0 |e Corresponding author |
| 245 | _ | _ | |a Silicon tunnel FET with average subthreshold slope of 55 mV/dec at low drain currents |
| 260 | _ | _ | |a Oxford [u.a.] |c 2018 |b Pergamon, Elsevier Science |
| 336 | 7 | _ | |a article |2 DRIVER |
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| 520 | _ | _ | |a In this paper we present a silicon tunnel FET based on line-tunneling to achieve better subthreshold performance. The fabricated device shows an on-current of Ion = 2.55 × 10−7 A/µm at Vds = Von = Vgs − Voff = −0.5 V for an Ioff = 1 nA/µm and an average SS of 55 mV/dec over two orders of magnitude of Id. Furthermore, the analog figures of merit have been calculated and show that the transconductance efficiency gm/Id beats the MOSFET performance at low currents. |
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| 700 | 1 | _ | |a von den Driesch, N. |0 P:(DE-Juel1)161247 |b 3 |u fzj |
| 700 | 1 | _ | |a Zhao, Q. T. |0 P:(DE-Juel1)128649 |b 4 |u fzj |
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| 773 | _ | _ | |a 10.1016/j.sse.2018.01.007 |g Vol. 143, p. 62 - 68 |0 PERI:(DE-600)2012825-3 |p 62 - 68 |t Solid state electronics |v 143 |y 2018 |x 0038-1101 |
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