%0 Journal Article
%A Lin, Jyi-Tsong
%A Wang, Tzu-Chi
%A Lee, Wei-Han
%A Yeh, Chih-Ting
%A Glass, Stefan
%A Zhao, Qing-Tai
%T Characteristics of Recessed-Gate TFETs With Line Tunneling
%J IEEE transactions on electron devices
%V 65
%N 2
%@ 1557-9646
%C New York, NY
%I IEEE
%M FZJ-2019-00017
%P 769 - 775
%D 2018
%X In this paper, we propose a recessed-gate tunneling field-effect transistor (TFET) to improve the on current of TFETs by increasing the tunnel area with line tunneling. We investigate the effects of the recessed-body thickness and the doping level on the device performance. For optimal device structures, our proposed n-TFET reaches 1.44 × 10 -6 A/μm of on current and 3.22 × 10 9 ON/OFF current ratio. A minimum subthreshold swing SS min = 28.3 mV/dec and an average swing SS avg = 59.8 mV/dec over seven orders of drain current are achieved. In addition, complementary TFET inverters show good noise margins of NM H = 65 mV (38.5 % V DD ) and NM L = 77 mV (32.5 % V DD ) and also a high voltage gain even at V DD = 0.2 V.
%F PUB:(DE-HGF)16
%9 Journal Article
%U <Go to ISI:>//WOS:000423124500058
%R 10.1109/TED.2017.2786215
%U https://juser.fz-juelich.de/record/859066