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@INPROCEEDINGS{Horst:859069,
      author       = {Horst, Fabian and Farokhnejad, Atieh and Graef, Michael and
                      Hosenfeld, Fabian and Luong, Gia Vinh and Liu, Chang and
                      Lime, Francois and Iniguez, Benjamin and Kloes, Alexander},
      collaboration = {Zhao, Qing-Tai},
      title        = {{DC}/{AC} {C}ompact {M}odeling of {TFET}s for {C}ircuit
                      {S}imulation of {L}ogic {C}ells {B}ased on an {A}nalytical
                      {P}hysics-{B}ased {F}ramework},
      publisher    = {IEEE},
      reportid     = {FZJ-2019-00020},
      pages        = {6-10},
      year         = {2017},
      comment      = {2017 Austrochip Workshop on Microelectronics (Austrochip) :
                      [Proceedings] - IEEE, 2017. - ISBN 978-1-5386-3583-4 -
                      doi:10.1109/Austrochip.2017.10},
      booktitle     = {2017 Austrochip Workshop on
                       Microelectronics (Austrochip) :
                       [Proceedings] - IEEE, 2017. - ISBN
                       978-1-5386-3583-4 -
                       doi:10.1109/Austrochip.2017.10},
      abstract     = {This paper presents a DC/AC compact model for double-gate
                      (DG) tunnel field-effect transistors (TFET) which is based
                      on a unified analytical modeling framework. The closed-form
                      model shows a good agreement with both, TCAD simulations and
                      measurements on test structures. A Verilog-A implementation
                      allows for a quick performance evaluation of the DC
                      performance of logic cells. Results of a complementary TFET
                      inverter are in good agreement to measurements. Simulations
                      of an 8T SRAM cell clearly show the critical influence of
                      the ambipolar behavior and leakage current on the
                      performance. The fundamental analytical modeling framework
                      provides deeper physical insight while considering
                      additional effects as trap-assisted tunneling (TAT),
                      junction profile steepness and hetero structures.},
      month         = {Oct},
      date          = {2017-10-12},
      organization  = {2017 25th Austrochip Workshop on
                       Microelectronics (Austrochip), Linz
                       (Austria), 12 Oct 2017 - 12 Oct 2017},
      cin          = {PGI-9},
      cid          = {I:(DE-Juel1)PGI-9-20110106},
      pnm          = {521 - Controlling Electron Charge-Based Phenomena
                      (POF3-521)},
      pid          = {G:(DE-HGF)POF3-521},
      typ          = {PUB:(DE-HGF)8 / PUB:(DE-HGF)7},
      UT           = {WOS:000427480800002},
      doi          = {10.1109/Austrochip.2017.10},
      url          = {https://juser.fz-juelich.de/record/859069},
}