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000859070 1001_ $$0P:(DE-Juel1)156277$$aLuong, G. V.$$b0
000859070 1112_ $$aESSDERC 2017 - 47th IEEE European Solid-State Device Research Conference (ESSDERC)$$cLeuven$$d2017-09-11 - 2017-09-14$$wBelgium
000859070 245__ $$aExperimental characterization of the static noise margins of strained silicon complementary tunnel-FET SRAM
000859070 260__ $$bIEEE$$c2017
000859070 29510 $$a2017 47th European Solid-State Device Research Conference (ESSDERC) : [Proceedings] - IEEE, 2017. - ISBN 978-1-5090-5978-2 - doi:10.1109/ESSDERC.2017.8066587
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000859070 520__ $$aHalf SRAM cells with strained Si nanowire complementary Tunnel-FETs (CTFET) have been fabricated to explore the capability of TFETs for 6T-SRAM. Static measurements on cells with outward faced n-TFET access transistors have been performed to determine the SRAM butterfly curves, allowing the assessment of cell functionality and stability. The forward p-i-n leakage at certain bias configuration of the access transistor may lead to malfunctioning storage operation, even without the contribution of the ambipolar behavior. Lowering the bit-line bias is found to mitigate such effect resulting in functional hold, read and write operation.
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000859070 7001_ $$0P:(DE-HGF)0$$aStrangio, S.$$b1
000859070 7001_ $$0P:(DE-Juel1)128639$$aTiedemann, Andreas$$b2$$ufzj
000859070 7001_ $$0P:(DE-Juel1)138772$$aBernardy, P.$$b3$$ufzj
000859070 7001_ $$0P:(DE-Juel1)128856$$aTrellenkamp, S.$$b4$$ufzj
000859070 7001_ $$0P:(DE-HGF)0$$aPalestri, P.$$b5
000859070 7001_ $$0P:(DE-Juel1)128609$$aMantl, S.$$b6$$ufzj
000859070 7001_ $$0P:(DE-Juel1)128649$$aZhao, Q. T.$$b7$$eCorresponding author
000859070 773__ $$a10.1109/ESSDERC.2017.8066587
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000859070 9141_ $$y2018
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