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024 7 _ |a 10.1109/ESSDERC.2017.8066587
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100 1 _ |a Luong, G. V.
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111 2 _ |a ESSDERC 2017 - 47th IEEE European Solid-State Device Research Conference (ESSDERC)
|c Leuven
|d 2017-09-11 - 2017-09-14
|w Belgium
245 _ _ |a Experimental characterization of the static noise margins of strained silicon complementary tunnel-FET SRAM
260 _ _ |c 2017
|b IEEE
295 1 0 |a 2017 47th European Solid-State Device Research Conference (ESSDERC) : [Proceedings] - IEEE, 2017. - ISBN 978-1-5090-5978-2 - doi:10.1109/ESSDERC.2017.8066587
300 _ _ |a 42-45
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520 _ _ |a Half SRAM cells with strained Si nanowire complementary Tunnel-FETs (CTFET) have been fabricated to explore the capability of TFETs for 6T-SRAM. Static measurements on cells with outward faced n-TFET access transistors have been performed to determine the SRAM butterfly curves, allowing the assessment of cell functionality and stability. The forward p-i-n leakage at certain bias configuration of the access transistor may lead to malfunctioning storage operation, even without the contribution of the ambipolar behavior. Lowering the bit-line bias is found to mitigate such effect resulting in functional hold, read and write operation.
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700 1 _ |a Strangio, S.
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700 1 _ |a Tiedemann, Andreas
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700 1 _ |a Trellenkamp, S.
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700 1 _ |a Palestri, P.
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700 1 _ |a Mantl, S.
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700 1 _ |a Zhao, Q. T.
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773 _ _ |a 10.1109/ESSDERC.2017.8066587
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