Contribution to a conference proceedings

FZJ-2019-00036

http://join2-wiki.gsi.de/foswiki/pub/Main/Artwork/join2_logo100x88.png Silicon tunnel FET with average subthreshold slope of 55mV/dec at low drain currents

Narimani, K. (Corresponding author)FZJ* ; Glass, S.FZJ* ; Rieger, T.FZJ* ; Bernardy, P.FZJ* ; von den Driesch, N.FZJ* ; Mantl, S.FZJ* ; Zhao, Q. T.FZJ*

2017
IEEE

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Please use a persistent id in citations: doi:10.1109/ULIS.2017.7962605

Abstract: In this paper we present a silicon tunnel FET based on line-tunneling to achieve better subthreshold performance. It is shown that the device achieves I on /I off ratio of 5×10 4 considering I on (V on = V Ioff -0.5V) = 0.8×10 -8 μA/μm and an average SS of 55mV/dec over two orders of magnitude of I d . Furthermore, the analog figures of merit have been calculated and show that the transconductance efficiency g m /I d beats the MOSFET performance at lower currents.

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Contributing Institute(s):

1. Halbleiter-Nanoelektronik (PGI-9)

Research Program(s):

1. 521 - Controlling Electron Charge-Based Phenomena (POF3-521) (POF3-521)

Appears in the scientific report 2018

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