%0 Conference Paper
%A Farokhnejad, A.
%A Graef, M.
%A Horst, F.
%A Liu, C.
%A Iniguez, B.
%A Lime, F.
%A Kloes, A.
%T Compact modeling of intrinsic capacitances in Double-Gate Tunnel-FETs
%I IEEE
%M FZJ-2019-00038
%P 1-4
%D 2017
%X In this paper a compact model for intrinsic capacitances for Tunnel field-effect transistors (TFETs) is presented. The model is derived from the carrier concentration and current flowing the channel of a Si Double-Gate (DG) n-type TFET. It represents a particularly good estimation of TFET capacitances and the flexibility of this model makes it possible to apply it for single-gate or p-type TFETs as well. To verify the model, the results are compared with TCAD Sentaurus simulations as well as measurement data. In both case model shows satisfying results.
%B 2017 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon (EUROSOI-ULIS)
%C 3 Apr 2017 - 5 Apr 2017, Athens (Greece)
Y2 3 Apr 2017 - 5 Apr 2017
M2 Athens, Greece
%F PUB:(DE-HGF)8
%9 Contribution to a conference proceedings
%R 10.1109/ULIS.2017.7962584
%U https://juser.fz-juelich.de/record/859087