TY  - CONF
AU  - Farokhnejad, A.
AU  - Graef, M.
AU  - Horst, F.
AU  - Liu, C.
AU  - Iniguez, B.
AU  - Lime, F.
AU  - Kloes, A.
TI  - Compact modeling of intrinsic capacitances in Double-Gate Tunnel-FETs
PB  - IEEE
M1  - FZJ-2019-00038
SP  - 1-4
PY  - 2017
AB  - In this paper a compact model for intrinsic capacitances for Tunnel field-effect transistors (TFETs) is presented. The model is derived from the carrier concentration and current flowing the channel of a Si Double-Gate (DG) n-type TFET. It represents a particularly good estimation of TFET capacitances and the flexibility of this model makes it possible to apply it for single-gate or p-type TFETs as well. To verify the model, the results are compared with TCAD Sentaurus simulations as well as measurement data. In both case model shows satisfying results.
T2  - 2017 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon (EUROSOI-ULIS)
CY  - 3 Apr 2017 - 5 Apr 2017, Athens (Greece)
Y2  - 3 Apr 2017 - 5 Apr 2017
M2  - Athens, Greece
LB  - PUB:(DE-HGF)8
DO  - DOI:10.1109/ULIS.2017.7962584
UR  - https://juser.fz-juelich.de/record/859087
ER  -