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024 7 _ |a 10.1109/ULIS.2017.7962584
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037 _ _ |a FZJ-2019-00038
100 1 _ |a Farokhnejad, A.
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|e Corresponding author
111 2 _ |a 2017 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon (EUROSOI-ULIS)
|c Athens
|d 2017-04-03 - 2017-04-05
|w Greece
245 _ _ |a Compact modeling of intrinsic capacitances in Double-Gate Tunnel-FETs
260 _ _ |c 2017
|b IEEE
300 _ _ |a 1-4
336 7 _ |a CONFERENCE_PAPER
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336 7 _ |a Conference Paper
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336 7 _ |a INPROCEEDINGS
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520 _ _ |a In this paper a compact model for intrinsic capacitances for Tunnel field-effect transistors (TFETs) is presented. The model is derived from the carrier concentration and current flowing the channel of a Si Double-Gate (DG) n-type TFET. It represents a particularly good estimation of TFET capacitances and the flexibility of this model makes it possible to apply it for single-gate or p-type TFETs as well. To verify the model, the results are compared with TCAD Sentaurus simulations as well as measurement data. In both case model shows satisfying results.
536 _ _ |a 521 - Controlling Electron Charge-Based Phenomena (POF3-521)
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700 1 _ |a Graef, M.
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700 1 _ |a Horst, F.
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700 1 _ |a Liu, C.
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700 1 _ |a Zhao, Q. T.
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700 1 _ |a Iniguez, B.
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700 1 _ |a Lime, F.
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700 1 _ |a Kloes, A.
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773 _ _ |a 10.1109/ULIS.2017.7962584
856 4 _ |u https://juser.fz-juelich.de/record/859087/files/07962584.pdf
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914 1 _ |y 2018
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