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@INPROCEEDINGS{Nielinger:859311,
      author       = {Nielinger, Dennis and Christ, Volker and Degenhardt,
                      Carsten and Geck, Lotte and Grewing, Christian and Kruth,
                      Andre and Liebau, Daniel and Muralidharan, Pavithra and
                      Schubert, Petra and Vliex, Patrick and Zambanini, Andre and
                      van Waasen, Stefan},
      title        = {{SQ}u{B}i{C}1: {A}n {I}ntegrated {C}ontrol {C}hip for
                      {S}emiconductor {S}pin {Q}ubits},
      reportid     = {FZJ-2019-00183},
      year         = {2018},
      abstract     = {In most quantum experiments nowadays the control and
                      readout electronics is placed at room temperature. The
                      number of qubits which can be operated with this approach is
                      severely limited by the number of interconnects and the
                      wiring between the qubit operating temperature level and the
                      room temperature level. At the Central Institute for
                      Electronic Systems at the Forschungszentrum Jülich we
                      develop and design scalable solutions for readout and
                      control of qubits for future use in quantum computers. Our
                      approach leverages the advances of state-of-the-art
                      commercial CMOS technologies while operating at
                      deep-cryogenic temperatures close to the actual qubit. We
                      designed and layouted a first chip for concept proof in a
                      commercial 65 nm CMOS process. This chip contains a
                      DC-digital-to-analog converter (DC-DAC), a pulse
                      digital-to-analog converter, a 500 MHz digitally controlled
                      current starved ring oscillator and a 20 GHz LC-oscillator.
                      The DC-DAC is operating in a voltage range between 0 V and 1
                      V. The pulse DAC operates at a sample rate of 250 MHz and
                      generates pulses in a range of 8 mV. In this presentation
                      the chip architecture will be discussed in detail and
                      corresponding simulation results will be shown.},
      month         = {Nov},
      date          = {2018-11-13},
      organization  = {Silicon Quantum Electronics Workshop
                       2018, Sydney (Australia), 13 Nov 2018 -
                       15 Nov 2018},
      subtyp        = {After Call},
      cin          = {ZEA-2},
      cid          = {I:(DE-Juel1)ZEA-2-20090406},
      pnm          = {524 - Controlling Collective States (POF3-524)},
      pid          = {G:(DE-HGF)POF3-524},
      typ          = {PUB:(DE-HGF)6},
      url          = {https://juser.fz-juelich.de/record/859311},
}