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| 001 | 859311 | ||
| 005 | 20250129092504.0 | ||
| 024 | 7 | _ | |a 2128/21202 |2 Handle |
| 037 | _ | _ | |a FZJ-2019-00183 |
| 041 | _ | _ | |a English |
| 100 | 1 | _ | |a Nielinger, Dennis |0 P:(DE-Juel1)168167 |b 0 |e Corresponding author |
| 111 | 2 | _ | |a Silicon Quantum Electronics Workshop 2018 |c Sydney |d 2018-11-13 - 2018-11-15 |w Australia |
| 245 | _ | _ | |a SQuBiC1: An Integrated Control Chip for Semiconductor Spin Qubits |
| 260 | _ | _ | |c 2018 |
| 336 | 7 | _ | |a Conference Paper |0 33 |2 EndNote |
| 336 | 7 | _ | |a Other |2 DataCite |
| 336 | 7 | _ | |a INPROCEEDINGS |2 BibTeX |
| 336 | 7 | _ | |a conferenceObject |2 DRIVER |
| 336 | 7 | _ | |a LECTURE_SPEECH |2 ORCID |
| 336 | 7 | _ | |a Conference Presentation |b conf |m conf |0 PUB:(DE-HGF)6 |s 1547621555_11586 |2 PUB:(DE-HGF) |x After Call |
| 520 | _ | _ | |a In most quantum experiments nowadays the control and readout electronics is placed at room temperature. The number of qubits which can be operated with this approach is severely limited by the number of interconnects and the wiring between the qubit operating temperature level and the room temperature level. At the Central Institute for Electronic Systems at the Forschungszentrum Jülich we develop and design scalable solutions for readout and control of qubits for future use in quantum computers. Our approach leverages the advances of state-of-the-art commercial CMOS technologies while operating at deep-cryogenic temperatures close to the actual qubit. We designed and layouted a first chip for concept proof in a commercial 65 nm CMOS process. This chip contains a DC-digital-to-analog converter (DC-DAC), a pulse digital-to-analog converter, a 500 MHz digitally controlled current starved ring oscillator and a 20 GHz LC-oscillator. The DC-DAC is operating in a voltage range between 0 V and 1 V. The pulse DAC operates at a sample rate of 250 MHz and generates pulses in a range of 8 mV. In this presentation the chip architecture will be discussed in detail and corresponding simulation results will be shown. |
| 536 | _ | _ | |a 524 - Controlling Collective States (POF3-524) |0 G:(DE-HGF)POF3-524 |c POF3-524 |f POF III |x 0 |
| 700 | 1 | _ | |a Christ, Volker |0 P:(DE-Juel1)171560 |b 1 |
| 700 | 1 | _ | |a Degenhardt, Carsten |0 P:(DE-Juel1)167475 |b 2 |
| 700 | 1 | _ | |a Geck, Lotte |0 P:(DE-Juel1)169123 |b 3 |
| 700 | 1 | _ | |a Grewing, Christian |0 P:(DE-Juel1)159350 |b 4 |
| 700 | 1 | _ | |a Kruth, Andre |0 P:(DE-Juel1)156521 |b 5 |
| 700 | 1 | _ | |a Liebau, Daniel |0 P:(DE-Juel1)169472 |b 6 |
| 700 | 1 | _ | |a Muralidharan, Pavithra |0 P:(DE-Juel1)162362 |b 7 |
| 700 | 1 | _ | |a Schubert, Petra |0 P:(DE-Juel1)174244 |b 8 |
| 700 | 1 | _ | |a Vliex, Patrick |0 P:(DE-Juel1)171680 |b 9 |
| 700 | 1 | _ | |a Zambanini, Andre |0 P:(DE-Juel1)145837 |b 10 |
| 700 | 1 | _ | |a van Waasen, Stefan |0 P:(DE-Juel1)142562 |b 11 |
| 856 | 4 | _ | |y OpenAccess |u https://juser.fz-juelich.de/record/859311/files/20181113_SQEW2018_SYDNEY_TALK.pdf |
| 856 | 4 | _ | |y OpenAccess |x pdfa |u https://juser.fz-juelich.de/record/859311/files/20181113_SQEW2018_SYDNEY_TALK.pdf?subformat=pdfa |
| 909 | C | O | |o oai:juser.fz-juelich.de:859311 |p openaire |p open_access |p VDB |p driver |
| 910 | 1 | _ | |a Forschungszentrum Jülich |0 I:(DE-588b)5008462-8 |k FZJ |b 0 |6 P:(DE-Juel1)168167 |
| 910 | 1 | _ | |a Forschungszentrum Jülich |0 I:(DE-588b)5008462-8 |k FZJ |b 1 |6 P:(DE-Juel1)171560 |
| 910 | 1 | _ | |a Forschungszentrum Jülich |0 I:(DE-588b)5008462-8 |k FZJ |b 2 |6 P:(DE-Juel1)167475 |
| 910 | 1 | _ | |a Forschungszentrum Jülich |0 I:(DE-588b)5008462-8 |k FZJ |b 3 |6 P:(DE-Juel1)169123 |
| 910 | 1 | _ | |a Forschungszentrum Jülich |0 I:(DE-588b)5008462-8 |k FZJ |b 4 |6 P:(DE-Juel1)159350 |
| 910 | 1 | _ | |a Forschungszentrum Jülich |0 I:(DE-588b)5008462-8 |k FZJ |b 5 |6 P:(DE-Juel1)156521 |
| 910 | 1 | _ | |a Forschungszentrum Jülich |0 I:(DE-588b)5008462-8 |k FZJ |b 6 |6 P:(DE-Juel1)169472 |
| 910 | 1 | _ | |a Forschungszentrum Jülich |0 I:(DE-588b)5008462-8 |k FZJ |b 7 |6 P:(DE-Juel1)162362 |
| 910 | 1 | _ | |a Forschungszentrum Jülich |0 I:(DE-588b)5008462-8 |k FZJ |b 8 |6 P:(DE-Juel1)174244 |
| 910 | 1 | _ | |a Forschungszentrum Jülich |0 I:(DE-588b)5008462-8 |k FZJ |b 9 |6 P:(DE-Juel1)171680 |
| 910 | 1 | _ | |a Forschungszentrum Jülich |0 I:(DE-588b)5008462-8 |k FZJ |b 10 |6 P:(DE-Juel1)145837 |
| 910 | 1 | _ | |a Forschungszentrum Jülich |0 I:(DE-588b)5008462-8 |k FZJ |b 11 |6 P:(DE-Juel1)142562 |
| 913 | 1 | _ | |a DE-HGF |b Key Technologies |l Future Information Technology - Fundamentals, Novel Concepts and Energy Efficiency (FIT) |1 G:(DE-HGF)POF3-520 |0 G:(DE-HGF)POF3-524 |2 G:(DE-HGF)POF3-500 |v Controlling Collective States |x 0 |4 G:(DE-HGF)POF |3 G:(DE-HGF)POF3 |
| 914 | 1 | _ | |y 2018 |
| 915 | _ | _ | |a OpenAccess |0 StatID:(DE-HGF)0510 |2 StatID |
| 920 | _ | _ | |l no |
| 920 | 1 | _ | |0 I:(DE-Juel1)ZEA-2-20090406 |k ZEA-2 |l Zentralinstitut für Elektronik |x 0 |
| 980 | 1 | _ | |a FullTexts |
| 980 | _ | _ | |a conf |
| 980 | _ | _ | |a VDB |
| 980 | _ | _ | |a UNRESTRICTED |
| 980 | _ | _ | |a I:(DE-Juel1)ZEA-2-20090406 |
| 981 | _ | _ | |a I:(DE-Juel1)PGI-4-20110106 |
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