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000859442 1001_ $$0P:(DE-Juel1)164418$$aParkalian, Nina$$b0$$eCorresponding author$$ufzj
000859442 1112_ $$a15th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD)$$cPrague$$d2018-07-02 - 2018-07-05$$wCzech Republic
000859442 245__ $$aModeling and Simulation of Digital Phase-Locked Loop in Simulink
000859442 260__ $$c2018
000859442 3367_ $$033$$2EndNote$$aConference Paper
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000859442 520__ $$aThis paper presents a high-level model for a digital phase-locked loop implemented in Simulink. This modeling enables the flexible and fast estimation of the design behavior and parameters before transistor-level implementation. The design includes a digital controlled oscillator that is defined using a linear s-domain model. Furthermore, the design of a time-to-digital converter based on oversampling and noise shaping is introduced to increase the effective resolution of the block. The simulation results of locking process, stability and phase noise verify the functionality of the model.
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000859442 7001_ $$0P:(DE-Juel1)156319$$aRobens, Markus$$b1$$ufzj
000859442 7001_ $$0P:(DE-Juel1)159350$$aGrewing, Christian$$b2$$ufzj
000859442 7001_ $$0P:(DE-Juel1)171560$$aChrist, Volker$$b3$$ufzj
000859442 7001_ $$0P:(DE-Juel1)169472$$aLiebau, Daniel$$b4$$ufzj
000859442 7001_ $$0P:(DE-Juel1)162362$$aMuralidharan, Pavithra$$b5$$ufzj
000859442 7001_ $$0P:(DE-Juel1)168167$$aNielinger, Dennis$$b6$$ufzj
000859442 7001_ $$0P:(DE-Juel1)128751$$aYegin, Ugur$$b7$$ufzj
000859442 7001_ $$0P:(DE-Juel1)145837$$aZambanini, Andre$$b8$$ufzj
000859442 7001_ $$0P:(DE-Juel1)142562$$avan Waasen, Stefan$$b9$$ufzj
000859442 8564_ $$uhttps://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=8434865
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000859442 9141_ $$y2018
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