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@INPROCEEDINGS{Parkalian:859442,
      author       = {Parkalian, Nina and Robens, Markus and Grewing, Christian
                      and Christ, Volker and Liebau, Daniel and Muralidharan,
                      Pavithra and Nielinger, Dennis and Yegin, Ugur and
                      Zambanini, Andre and van Waasen, Stefan},
      title        = {{M}odeling and {S}imulation of {D}igital {P}hase-{L}ocked
                      {L}oop in {S}imulink},
      reportid     = {FZJ-2019-00298},
      year         = {2018},
      abstract     = {This paper presents a high-level model for a digital
                      phase-locked loop implemented in Simulink. This modeling
                      enables the flexible and fast estimation of the design
                      behavior and parameters before transistor-level
                      implementation. The design includes a digital controlled
                      oscillator that is defined using a linear s-domain model.
                      Furthermore, the design of a time-to-digital converter based
                      on oversampling and noise shaping is introduced to increase
                      the effective resolution of the block. The simulation
                      results of locking process, stability and phase noise verify
                      the functionality of the model.},
      month         = {Jul},
      date          = {2018-07-02},
      organization  = {15th International Conference on
                       Synthesis, Modeling, Analysis and
                       Simulation Methods and Applications to
                       Circuit Design (SMACD), Prague (Czech
                       Republic), 2 Jul 2018 - 5 Jul 2018},
      subtyp        = {After Call},
      cin          = {ZEA-2},
      cid          = {I:(DE-Juel1)ZEA-2-20090406},
      pnm          = {899 - ohne Topic (POF3-899)},
      pid          = {G:(DE-HGF)POF3-899},
      typ          = {PUB:(DE-HGF)6},
      url          = {https://juser.fz-juelich.de/record/859442},
}