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@PHDTHESIS{Parkalian:862375,
      author       = {Parkalian, Nina},
      title        = {{C}onfigurable frequency synthesizer for large scale
                      physics experiments},
      volume       = {56},
      school       = {Universität Duisburg},
      type         = {Dissertation},
      address      = {Jülich},
      publisher    = {Forschungszentrum Jülich GmbH Zentralbibliothek, Verlag},
      reportid     = {FZJ-2019-02708},
      isbn         = {978-3-95806-393-8},
      series       = {Schriften des Forschungszentrums Jülich. Reihe Information
                      / Information},
      pages        = {xxi, 114 S.},
      year         = {2019},
      note         = {Universität Duisburg, Diss., 2019},
      abstract     = {This thesis describes the design and implementation of
                      frequency synthesizers for the ”Jiangmen Underground
                      Neutrino Observatory (JUNO)” project as a physical
                      experiment. The fully integrated analog phase-locked loop
                      (PLL) based frequency synthesizer is intended to generate
                      the sampling clocks for the analog-to-digital converters
                      (ADC) and digital signal processing (DSP) part. They are
                      employed in the read-out electronics to be used in a
                      neutrino experiment. The proposed design was fabricated in
                      65 nm CMOS technology. The design provides the best
                      compromise between noise, power consumption and area for a
                      highly reliable and configurable operation based on the
                      application requirements. The design procedure for the PLL
                      architecture and different sub-blocks are presented. A 4 GHz
                      LC-based voltage controlled oscillator (VCO) is suggested
                      for the low noise operation while providing an optimum
                      tuning range to increase the linearity and frequency
                      coverage in case of process-voltage-temperature (PVT)
                      changes. Furthermore, a novel technique for the amplitude
                      regulation is suggested to detect amplitude errors at the
                      outputs of the VCO and provide an optimized range for the
                      amplitude for a low noise and reliable design. In addition,
                      a new approach for the charge pump is introduced that
                      suppresses the associated current mismatch problem of
                      conventional structures. This minimizes the static phase
                      error at the input of the PLL that causes spurs at the
                      output. The measurement results of the analog PLL show very
                      good performance of the structure based on the required
                      specifications and confirm the simulations. The total power
                      consumption for the PLL core equals to 18.5 mW at 1.8 V
                      supply for the VCO and 1 V supply for the other blocks.
                      [...]},
      cin          = {ZEA-2},
      cid          = {I:(DE-Juel1)ZEA-2-20090406},
      pnm          = {899 - ohne Topic (POF3-899)},
      pid          = {G:(DE-HGF)POF3-899},
      typ          = {PUB:(DE-HGF)3 / PUB:(DE-HGF)11},
      urn          = {urn:nbn:de:0001-2019050207},
      url          = {https://juser.fz-juelich.de/record/862375},
}