TY  - JOUR
AU  - Acharya, Abhishek
AU  - Solanki, A. B.
AU  - Glass, S.
AU  - Zhao, Qing-Tai
AU  - Anand, Bulusu
TI  - Impact of Gate–Source Overlap on the Device/Circuit Analog Performance of Line TFETs
JO  - IEEE transactions on electron devices
VL  - 66
IS  - 9
SN  - 1557-9646
CY  - New York, NY
PB  - IEEE
M1  - FZJ-2019-04358
SP  - 4081 - 4086
PY  - 2019
AB  - The gate–source overlap length ( ${L}_{{\text {OV}}}$ ) in the line tunneling FET (L-TFET) can be used as a design parameter to improve the analog circuit performance. In this paper, we investigate the drain current ( ${I}_{D}$ ) dependence on ${L}_{{\text {OV}}}$ , considering the electrostatics of the gate–source overlap region. It is observed that ${I}_{D}$ increases with ${L}_{{\text {OV}}}$ exhibiting a nonlinear behavior. This happens as the impact of the lateral electric field at the far end of the tunnel junction reduces, thereby reducing the tunneling rate. Based on our semiempirical physical ${I}_{D}$ – ${L}_{{\text {OV}}}$ model, a novel ${L}_{{\text {OV}}}$ variation-aware small signal model for L-TFET is also proposed. The output resistance and the gate–drain capacitance remain almost independent of ${L}_{{\text {OV}}}$ in the saturation regime. The gate–source capacitance and the transconductance linearly increase with ${L}_{{\text {OV}}}$ . A common source amplifier is demonstrated with ~2.4 times increase in the voltage gain when ${L}_{{\text {OV}}}$ is increased from 20 to 50 nm, with a penalty of ~10% in the bandwidth. We observe that it is not possible to achieve the gain similar to one obtained using 2.5 times increase in ${L}_{{\text {OV}}}$ even after increasing the device width five times. However, the bandwidth reduces 30% at such width owing to an increase in the gate capacitances.
LB  - PUB:(DE-HGF)16
UR  - <Go to ISI:>//WOS:000482583200059
DO  - DOI:10.1109/TED.2019.2927001
UR  - https://juser.fz-juelich.de/record/864660
ER  -