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@ARTICLE{Acharya:864660,
      author       = {Acharya, Abhishek and Solanki, A. B. and Glass, S. and
                      Zhao, Qing-Tai and Anand, Bulusu},
      title        = {{I}mpact of {G}ate–{S}ource {O}verlap on the
                      {D}evice/{C}ircuit {A}nalog {P}erformance of {L}ine {TFET}s},
      journal      = {IEEE transactions on electron devices},
      volume       = {66},
      number       = {9},
      issn         = {1557-9646},
      address      = {New York, NY},
      publisher    = {IEEE},
      reportid     = {FZJ-2019-04358},
      pages        = {4081 - 4086},
      year         = {2019},
      abstract     = {The gate–source overlap length ( ${L}_{{\text {OV}}}$ )
                      in the line tunneling FET (L-TFET) can be used as a design
                      parameter to improve the analog circuit performance. In this
                      paper, we investigate the drain current ( ${I}_{D}$ )
                      dependence on ${L}_{{\text {OV}}}$ , considering the
                      electrostatics of the gate–source overlap region. It is
                      observed that ${I}_{D}$ increases with ${L}_{{\text {OV}}}$
                      exhibiting a nonlinear behavior. This happens as the impact
                      of the lateral electric field at the far end of the tunnel
                      junction reduces, thereby reducing the tunneling rate. Based
                      on our semiempirical physical ${I}_{D}$ – ${L}_{{\text
                      {OV}}}$ model, a novel ${L}_{{\text {OV}}}$ variation-aware
                      small signal model for L-TFET is also proposed. The output
                      resistance and the gate–drain capacitance remain almost
                      independent of ${L}_{{\text {OV}}}$ in the saturation
                      regime. The gate–source capacitance and the
                      transconductance linearly increase with ${L}_{{\text {OV}}}$
                      . A common source amplifier is demonstrated with ~2.4 times
                      increase in the voltage gain when ${L}_{{\text {OV}}}$ is
                      increased from 20 to 50 nm, with a penalty of ~10\% in the
                      bandwidth. We observe that it is not possible to achieve the
                      gain similar to one obtained using 2.5 times increase in
                      ${L}_{{\text {OV}}}$ even after increasing the device width
                      five times. However, the bandwidth reduces 30\% at such
                      width owing to an increase in the gate capacitances.},
      cin          = {PGI-9},
      ddc          = {620},
      cid          = {I:(DE-Juel1)PGI-9-20110106},
      pnm          = {521 - Controlling Electron Charge-Based Phenomena
                      (POF3-521)},
      pid          = {G:(DE-HGF)POF3-521},
      typ          = {PUB:(DE-HGF)16},
      UT           = {WOS:000482583200059},
      doi          = {10.1109/TED.2019.2927001},
      url          = {https://juser.fz-juelich.de/record/864660},
}