%0 Journal Article
%A Siemon, A.
%A Drabinski, R.
%A Schultis, M. J.
%A Hu, X.
%A Linn, E.
%A Heittmann, A.
%A Waser, R.
%A Querlioz, D.
%A Menzel, S.
%A Friedman, J. S.
%T Stateful Three-Input Logic with Memristive Switches
%J Scientific reports
%V 9
%N 1
%@ 2045-2322
%C [London]
%I Macmillan Publishers Limited, part of Springer Nature
%M FZJ-2019-04815
%P 14618
%D 2019
%X Memristive switches are able to act as both storage and computing elements, which make them an excellent candidate for beyond-CMOS computing. In this paper, multi-input memristive switch logic is proposed, which enables the function X OR (Y NOR Z) to be performed in a single-step with three memristive switches. This ORNOR logic gate increases the capabilities of memristive switches, improving the overall system efficiency of a memristive switch-based computing architecture. Additionally, a computing system architecture and clocking scheme are proposed to further utilize memristive switching for computation. The system architecture is based on a design where multiple computational function blocks are interconnected and controlled by a master clock that synchronizes system data processing and transfer. The clocking steps to perform a full adder with the ORNOR gate are presented along with simulation results using a physics-based model. The full adder function block is integrated into the system architecture to realize a 64-bit full adder, which is also demonstrated through simulation.
%F PUB:(DE-HGF)16
%9 Journal Article
%$ pmid:31602003
%U <Go to ISI:>//WOS:000489555900012
%R 10.1038/s41598-019-51039-6
%U https://juser.fz-juelich.de/record/865313