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000865313 245__ $$aStateful Three-Input Logic with Memristive Switches
000865313 260__ $$a[London]$$bMacmillan Publishers Limited, part of Springer Nature$$c2019
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000865313 520__ $$aMemristive switches are able to act as both storage and computing elements, which make them an excellent candidate for beyond-CMOS computing. In this paper, multi-input memristive switch logic is proposed, which enables the function X OR (Y NOR Z) to be performed in a single-step with three memristive switches. This ORNOR logic gate increases the capabilities of memristive switches, improving the overall system efficiency of a memristive switch-based computing architecture. Additionally, a computing system architecture and clocking scheme are proposed to further utilize memristive switching for computation. The system architecture is based on a design where multiple computational function blocks are interconnected and controlled by a master clock that synchronizes system data processing and transfer. The clocking steps to perform a full adder with the ORNOR gate are presented along with simulation results using a physics-based model. The full adder function block is integrated into the system architecture to realize a 64-bit full adder, which is also demonstrated through simulation.
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000865313 7001_ $$0P:(DE-HGF)0$$aDrabinski, R.$$b1
000865313 7001_ $$0P:(DE-HGF)0$$aSchultis, M. J.$$b2
000865313 7001_ $$00000-0002-7337-6637$$aHu, X.$$b3
000865313 7001_ $$0P:(DE-Juel1)143695$$aLinn, E.$$b4
000865313 7001_ $$0P:(DE-Juel1)174220$$aHeittmann, A.$$b5$$ufzj
000865313 7001_ $$0P:(DE-Juel1)131022$$aWaser, R.$$b6$$ufzj
000865313 7001_ $$0P:(DE-HGF)0$$aQuerlioz, D.$$b7
000865313 7001_ $$0P:(DE-Juel1)158062$$aMenzel, S.$$b8$$eCorresponding author
000865313 7001_ $$00000-0001-9847-4455$$aFriedman, J. S.$$b9
000865313 773__ $$0PERI:(DE-600)2615211-3$$a10.1038/s41598-019-51039-6$$gVol. 9, no. 1, p. 14618$$n1$$p14618$$tScientific reports$$v9$$x2045-2322$$y2019
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