TY  - JOUR
AU  - Siemon, A.
AU  - Drabinski, R.
AU  - Schultis, M. J.
AU  - Hu, X.
AU  - Linn, E.
AU  - Heittmann, A.
AU  - Waser, R.
AU  - Querlioz, D.
AU  - Menzel, S.
AU  - Friedman, J. S.
TI  - Stateful Three-Input Logic with Memristive Switches
JO  - Scientific reports
VL  - 9
IS  - 1
SN  - 2045-2322
CY  - [London]
PB  - Macmillan Publishers Limited, part of Springer Nature
M1  - FZJ-2019-04815
SP  - 14618
PY  - 2019
AB  - Memristive switches are able to act as both storage and computing elements, which make them an excellent candidate for beyond-CMOS computing. In this paper, multi-input memristive switch logic is proposed, which enables the function X OR (Y NOR Z) to be performed in a single-step with three memristive switches. This ORNOR logic gate increases the capabilities of memristive switches, improving the overall system efficiency of a memristive switch-based computing architecture. Additionally, a computing system architecture and clocking scheme are proposed to further utilize memristive switching for computation. The system architecture is based on a design where multiple computational function blocks are interconnected and controlled by a master clock that synchronizes system data processing and transfer. The clocking steps to perform a full adder with the ORNOR gate are presented along with simulation results using a physics-based model. The full adder function block is integrated into the system architecture to realize a 64-bit full adder, which is also demonstrated through simulation.
LB  - PUB:(DE-HGF)16
C6  - pmid:31602003
UR  - <Go to ISI:>//WOS:000489555900012
DO  - DOI:10.1038/s41598-019-51039-6
UR  - https://juser.fz-juelich.de/record/865313
ER  -