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@ARTICLE{Siemon:865313,
      author       = {Siemon, A. and Drabinski, R. and Schultis, M. J. and Hu, X.
                      and Linn, E. and Heittmann, A. and Waser, R. and Querlioz,
                      D. and Menzel, S. and Friedman, J. S.},
      title        = {{S}tateful {T}hree-{I}nput {L}ogic with {M}emristive
                      {S}witches},
      journal      = {Scientific reports},
      volume       = {9},
      number       = {1},
      issn         = {2045-2322},
      address      = {[London]},
      publisher    = {Macmillan Publishers Limited, part of Springer Nature},
      reportid     = {FZJ-2019-04815},
      pages        = {14618},
      year         = {2019},
      abstract     = {Memristive switches are able to act as both storage and
                      computing elements, which make them an excellent candidate
                      for beyond-CMOS computing. In this paper, multi-input
                      memristive switch logic is proposed, which enables the
                      function X OR (Y NOR Z) to be performed in a single-step
                      with three memristive switches. This ORNOR logic gate
                      increases the capabilities of memristive switches, improving
                      the overall system efficiency of a memristive switch-based
                      computing architecture. Additionally, a computing system
                      architecture and clocking scheme are proposed to further
                      utilize memristive switching for computation. The system
                      architecture is based on a design where multiple
                      computational function blocks are interconnected and
                      controlled by a master clock that synchronizes system data
                      processing and transfer. The clocking steps to perform a
                      full adder with the ORNOR gate are presented along with
                      simulation results using a physics-based model. The full
                      adder function block is integrated into the system
                      architecture to realize a 64-bit full adder, which is also
                      demonstrated through simulation.},
      cin          = {PGI-7 / JARA-FIT / PGI-10 / PTJ-EGF},
      ddc          = {600},
      cid          = {I:(DE-Juel1)PGI-7-20110106 / $I:(DE-82)080009_20140620$ /
                      I:(DE-Juel1)PGI-10-20170113 / I:(DE-Juel1)PTJ-EGF-20140730},
      pnm          = {521 - Controlling Electron Charge-Based Phenomena
                      (POF3-521)},
      pid          = {G:(DE-HGF)POF3-521},
      typ          = {PUB:(DE-HGF)16},
      pubmed       = {pmid:31602003},
      UT           = {WOS:000489555900012},
      doi          = {10.1038/s41598-019-51039-6},
      url          = {https://juser.fz-juelich.de/record/865313},
}