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| Hauptseite > Publikationsdatenbank > Stateful Three-Input Logic with Memristive Switches > print |
| 001 | 865313 | ||
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| 245 | _ | _ | |a Stateful Three-Input Logic with Memristive Switches |
| 260 | _ | _ | |a [London] |c 2019 |b Macmillan Publishers Limited, part of Springer Nature |
| 336 | 7 | _ | |a article |2 DRIVER |
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| 520 | _ | _ | |a Memristive switches are able to act as both storage and computing elements, which make them an excellent candidate for beyond-CMOS computing. In this paper, multi-input memristive switch logic is proposed, which enables the function X OR (Y NOR Z) to be performed in a single-step with three memristive switches. This ORNOR logic gate increases the capabilities of memristive switches, improving the overall system efficiency of a memristive switch-based computing architecture. Additionally, a computing system architecture and clocking scheme are proposed to further utilize memristive switching for computation. The system architecture is based on a design where multiple computational function blocks are interconnected and controlled by a master clock that synchronizes system data processing and transfer. The clocking steps to perform a full adder with the ORNOR gate are presented along with simulation results using a physics-based model. The full adder function block is integrated into the system architecture to realize a 64-bit full adder, which is also demonstrated through simulation. |
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| 700 | 1 | _ | |a Menzel, S. |0 P:(DE-Juel1)158062 |b 8 |e Corresponding author |
| 700 | 1 | _ | |a Friedman, J. S. |0 0000-0001-9847-4455 |b 9 |
| 773 | _ | _ | |a 10.1038/s41598-019-51039-6 |g Vol. 9, no. 1, p. 14618 |0 PERI:(DE-600)2615211-3 |n 1 |p 14618 |t Scientific reports |v 9 |y 2019 |x 2045-2322 |
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