%0 Conference Paper
%A Degenhardt, C.
%A Artanov, A.
%A Geck, L.
%A Grewing, C.
%A Kruth, A.
%A Nielinger, D.
%A Vliex, P.
%A Zambanini, A.
%A van Waasen, S.
%T Systems Engineering of Cryogenic CMOS Electronics for Scalable Quantum Computers
%I IEEE
%M FZJ-2020-00914
%P 1 - 5
%D 2019
%X We report on our systems engineering activities concerning cryogenic CMOS electronics as building blocks for scalable quantum computers. Following the V-model of engineering, the topic is approached both in top-down and in bottom-up fashion. We show the main results from the top-down study using system modeling and simulations. In a bottom-up fashion, a prototype chip was designed and implemented in a commercial 65nm CMOS process. The chip contains a DC digital-to-analog-converter (DC-DAC) and a Pulse-DAC as building blocks for an integrated quantum bit control. The DC-DAC is able to tune a qubit into its operating point. The Pulse-DAC generates pulse patterns with 250MHz sampling frequency to perform gate operations on a qubit.
%B 2019 IEEE International Symposium on Circuits and Systems (ISCAS)
%C 26 May 2019 - 29 May 2019, Sapporo (Japan)
Y2 26 May 2019 - 29 May 2019
M2 Sapporo, Japan
%F PUB:(DE-HGF)8
%9 Contribution to a conference proceedings
%R 10.1109/ISCAS.2019.8702442
%U https://juser.fz-juelich.de/record/873691