Hauptseite > Publikationsdatenbank > Systems Engineering of Cryogenic CMOS Electronics for Scalable Quantum Computers > print

001     873691
005     20250129092443.0
024 7 _ |a 10.1109/ISCAS.2019.8702442
|2 doi
037 _ _ |a FZJ-2020-00914
100 1 _ |a Degenhardt, C.
|0 P:(DE-Juel1)167475
|b 0
|u fzj
111 2 _ |a 2019 IEEE International Symposium on Circuits and Systems (ISCAS)
|c Sapporo
|d 2019-05-26 - 2019-05-29
|w Japan
245 _ _ |a Systems Engineering of Cryogenic CMOS Electronics for Scalable Quantum Computers
260 _ _ |c 2019
|b IEEE
300 _ _ |a 1 - 5
336 7 _ |a CONFERENCE_PAPER
|2 ORCID
336 7 _ |a Conference Paper
|0 33
|2 EndNote
336 7 _ |a INPROCEEDINGS
|2 BibTeX
336 7 _ |a conferenceObject
|2 DRIVER
336 7 _ |a Output Types/Conference Paper
|2 DataCite
336 7 _ |a Contribution to a conference proceedings
|b contrib
|m contrib
|0 PUB:(DE-HGF)8
|s 1580989877_22020
|2 PUB:(DE-HGF)
520 _ _ |a We report on our systems engineering activities concerning cryogenic CMOS electronics as building blocks for scalable quantum computers. Following the V-model of engineering, the topic is approached both in top-down and in bottom-up fashion. We show the main results from the top-down study using system modeling and simulations. In a bottom-up fashion, a prototype chip was designed and implemented in a commercial 65nm CMOS process. The chip contains a DC digital-to-analog-converter (DC-DAC) and a Pulse-DAC as building blocks for an integrated quantum bit control. The DC-DAC is able to tune a qubit into its operating point. The Pulse-DAC generates pulse patterns with 250MHz sampling frequency to perform gate operations on a qubit.
536 _ _ |a 524 - Controlling Collective States (POF3-524)
|0 G:(DE-HGF)POF3-524
|c POF3-524
|f POF III
|x 0
588 _ _ |a Dataset connected to CrossRef Conference
700 1 _ |a Artanov, A.
|0 P:(DE-Juel1)174165
|b 1
|u fzj
700 1 _ |a Geck, L.
|0 P:(DE-Juel1)169123
|b 2
|u fzj
700 1 _ |a Grewing, C.
|0 P:(DE-Juel1)159350
|b 3
|u fzj
700 1 _ |a Kruth, A.
|0 P:(DE-Juel1)156521
|b 4
|u fzj
700 1 _ |a Nielinger, D.
|0 P:(DE-Juel1)168167
|b 5
|u fzj
700 1 _ |a Vliex, P.
|0 P:(DE-Juel1)171680
|b 6
|u fzj
700 1 _ |a Zambanini, A.
|0 P:(DE-Juel1)145837
|b 7
|u fzj
700 1 _ |a van Waasen, S.
|0 P:(DE-Juel1)142562
|b 8
|u fzj
773 _ _ |a 10.1109/ISCAS.2019.8702442
856 4 _ |u https://juser.fz-juelich.de/record/873691/files/08702442.pdf
|y Restricted
856 4 _ |u https://juser.fz-juelich.de/record/873691/files/08702442.pdf?subformat=pdfa
|x pdfa
|y Restricted
909 C O |o oai:juser.fz-juelich.de:873691
|p VDB
910 1 _ |a Forschungszentrum Jülich
|0 I:(DE-588b)5008462-8
|k FZJ
|b 0
|6 P:(DE-Juel1)167475
910 1 _ |a Forschungszentrum Jülich
|0 I:(DE-588b)5008462-8
|k FZJ
|b 1
|6 P:(DE-Juel1)174165
910 1 _ |a Forschungszentrum Jülich
|0 I:(DE-588b)5008462-8
|k FZJ
|b 2
|6 P:(DE-Juel1)169123
910 1 _ |a Forschungszentrum Jülich
|0 I:(DE-588b)5008462-8
|k FZJ
|b 3
|6 P:(DE-Juel1)159350
910 1 _ |a Forschungszentrum Jülich
|0 I:(DE-588b)5008462-8
|k FZJ
|b 4
|6 P:(DE-Juel1)156521
910 1 _ |a Forschungszentrum Jülich
|0 I:(DE-588b)5008462-8
|k FZJ
|b 5
|6 P:(DE-Juel1)168167
910 1 _ |a Forschungszentrum Jülich
|0 I:(DE-588b)5008462-8
|k FZJ
|b 6
|6 P:(DE-Juel1)171680
910 1 _ |a Forschungszentrum Jülich
|0 I:(DE-588b)5008462-8
|k FZJ
|b 7
|6 P:(DE-Juel1)145837
910 1 _ |a Forschungszentrum Jülich
|0 I:(DE-588b)5008462-8
|k FZJ
|b 8
|6 P:(DE-Juel1)142562
913 1 _ |a DE-HGF
|b Key Technologies
|l Future Information Technology - Fundamentals, Novel Concepts and Energy Efficiency (FIT)
|1 G:(DE-HGF)POF3-520
|0 G:(DE-HGF)POF3-524
|2 G:(DE-HGF)POF3-500
|v Controlling Collective States
|x 0
|4 G:(DE-HGF)POF
|3 G:(DE-HGF)POF3
914 1 _ |y 2019
920 1 _ |0 I:(DE-Juel1)ZEA-2-20090406
|k ZEA-2
|l Zentralinstitut für Elektronik
|x 0
980 _ _ |a contrib
980 _ _ |a VDB
980 _ _ |a I:(DE-Juel1)ZEA-2-20090406
980 _ _ |a UNRESTRICTED
981 _ _ |a I:(DE-Juel1)PGI-4-20110106

LibraryCollectionCLSMajorCLSMinorLanguageAuthor
Marc 21