%0 Journal Article
%A Liu, Mingshan
%A Scholz, Stefan
%A Hardtdegen, Alexander
%A Bae, Jin Hee
%A Hartmann, Jean-Michel
%A Knoch, Joachim
%A Grutzmacher, Detlev
%A Buca, Dan
%A Zhao, Qing-Tai
%T Vertical Ge Gate-All-Around Nanowire pMOSFETs With a Diameter Down to 20 nm
%J IEEE electron device letters
%V 41
%N 4
%@ 1558-0563
%C New York, NY
%I IEEE
%M FZJ-2020-01582
%P 533 - 536
%D 2020
%X In this work, we demonstrate vertical Ge gate-all-around (GAA) nanowire pMOSFETs fabricated with a CMOS compatible top-down approach. Vertical Ge nanowires with diameters down to 20 nm and an aspect ratio of ~11 were achieved by optimized Cl 2 -based dry etching and self-limiting digital etching. Employing a GAA architecture, post-oxidation passivation and NiGe contacts, high performance Ge nanowire pMOSFETs exhibit low SS of 66 mV/dec, small DIBL of 35 mV/V and a high $\text {I}_{ \mathrm{\scriptscriptstyle ON}}/\text{I}_{ \mathrm{\scriptscriptstyle OFF}}$ ratio of ${2.1}\times {10}^{{6}}$ . The electrical behavior was also studied with temperature-dependent measurements. The deviation between the experimental SS and the ideal kT/q $\cdot $ ln10 values stems from the density of interface traps $(\text {D}_{\text {it}})$ . Our measurements suggest that lowering the top contact resistance is a key to further performance improvement of vertical Ge GAA nanowire transistors.
%F PUB:(DE-HGF)16
%9 Journal Article
%U <Go to ISI:>//WOS:000522206300002
%R 10.1109/LED.2020.2971034
%U https://juser.fz-juelich.de/record/874666